From 3bd303f204a59ed950934f5da4c299a8be33b363 Mon Sep 17 00:00:00 2001 From: Joel Challis Date: Mon, 2 Sep 2024 03:48:17 +0100 Subject: Remove `arm_atsam` platform (#24337) --- .../packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h | 7226 -------------------- .../arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h | 223 - .../arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h | 1899 ----- .../packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h | 2103 ------ lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt | 201 - .../SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld | 185 - .../SAMD51_DFP/1.0.70/include/component-version.h | 65 - .../atmel/SAMD51_DFP/1.0.70/include/component/ac.h | 598 -- .../SAMD51_DFP/1.0.70/include/component/adc.h | 871 --- .../SAMD51_DFP/1.0.70/include/component/aes.h | 375 - .../SAMD51_DFP/1.0.70/include/component/can.h | 3207 --------- .../SAMD51_DFP/1.0.70/include/component/ccl.h | 228 - .../SAMD51_DFP/1.0.70/include/component/cmcc.h | 357 - .../SAMD51_DFP/1.0.70/include/component/dac.h | 544 -- .../SAMD51_DFP/1.0.70/include/component/dmac.h | 1416 ---- .../SAMD51_DFP/1.0.70/include/component/dsu.h | 1244 ---- .../SAMD51_DFP/1.0.70/include/component/eic.h | 497 -- .../SAMD51_DFP/1.0.70/include/component/evsys.h | 587 -- .../SAMD51_DFP/1.0.70/include/component/freqm.h | 233 - .../SAMD51_DFP/1.0.70/include/component/gclk.h | 272 - .../SAMD51_DFP/1.0.70/include/component/hmatrixb.h | 84 - .../SAMD51_DFP/1.0.70/include/component/i2s.h | 747 -- .../SAMD51_DFP/1.0.70/include/component/icm.h | 582 -- .../SAMD51_DFP/1.0.70/include/component/mclk.h | 474 -- .../SAMD51_DFP/1.0.70/include/component/nvmctrl.h | 861 --- .../1.0.70/include/component/osc32kctrl.h | 303 - .../SAMD51_DFP/1.0.70/include/component/oscctrl.h | 793 --- .../SAMD51_DFP/1.0.70/include/component/pac.h | 674 -- .../SAMD51_DFP/1.0.70/include/component/pcc.h | 251 - .../SAMD51_DFP/1.0.70/include/component/pdec.h | 726 -- .../atmel/SAMD51_DFP/1.0.70/include/component/pm.h | 261 - .../SAMD51_DFP/1.0.70/include/component/port.h | 414 -- .../SAMD51_DFP/1.0.70/include/component/qspi.h | 528 -- .../SAMD51_DFP/1.0.70/include/component/ramecc.h | 178 - .../SAMD51_DFP/1.0.70/include/component/rstc.h | 115 - .../SAMD51_DFP/1.0.70/include/component/rtc.h | 2098 ------ .../SAMD51_DFP/1.0.70/include/component/sdhc.h | 2599 ------- .../SAMD51_DFP/1.0.70/include/component/sercom.h | 1680 ----- .../SAMD51_DFP/1.0.70/include/component/supc.h | 554 -- .../SAMD51_DFP/1.0.70/include/component/tal.h | 1842 ----- .../atmel/SAMD51_DFP/1.0.70/include/component/tc.h | 851 --- .../SAMD51_DFP/1.0.70/include/component/tcc.h | 1762 ----- .../SAMD51_DFP/1.0.70/include/component/trng.h | 172 - .../SAMD51_DFP/1.0.70/include/component/usb.h | 1777 ----- .../SAMD51_DFP/1.0.70/include/component/wdt.h | 300 - .../atmel/SAMD51_DFP/1.0.70/include/instance/ac.h | 79 - .../SAMD51_DFP/1.0.70/include/instance/adc0.h | 99 - .../SAMD51_DFP/1.0.70/include/instance/adc1.h | 100 - .../atmel/SAMD51_DFP/1.0.70/include/instance/aes.h | 105 - .../SAMD51_DFP/1.0.70/include/instance/can0.h | 153 - .../SAMD51_DFP/1.0.70/include/instance/can1.h | 151 - .../atmel/SAMD51_DFP/1.0.70/include/instance/ccl.h | 57 - .../SAMD51_DFP/1.0.70/include/instance/cmcc.h | 61 - .../atmel/SAMD51_DFP/1.0.70/include/instance/dac.h | 88 - .../SAMD51_DFP/1.0.70/include/instance/dmac.h | 596 -- .../atmel/SAMD51_DFP/1.0.70/include/instance/dsu.h | 121 - .../atmel/SAMD51_DFP/1.0.70/include/instance/eic.h | 73 - .../SAMD51_DFP/1.0.70/include/instance/evsys.h | 722 -- .../SAMD51_DFP/1.0.70/include/instance/freqm.h | 59 - .../SAMD51_DFP/1.0.70/include/instance/gclk.h | 191 - .../SAMD51_DFP/1.0.70/include/instance/hmatrix.h | 133 - .../atmel/SAMD51_DFP/1.0.70/include/instance/i2s.h | 81 - .../atmel/SAMD51_DFP/1.0.70/include/instance/icm.h | 77 - .../SAMD51_DFP/1.0.70/include/instance/mclk.h | 61 - .../SAMD51_DFP/1.0.70/include/instance/nvmctrl.h | 75 - .../1.0.70/include/instance/osc32kctrl.h | 59 - .../SAMD51_DFP/1.0.70/include/instance/oscctrl.h | 130 - .../atmel/SAMD51_DFP/1.0.70/include/instance/pac.h | 69 - .../atmel/SAMD51_DFP/1.0.70/include/instance/pcc.h | 58 - .../SAMD51_DFP/1.0.70/include/instance/pdec.h | 80 - .../atmel/SAMD51_DFP/1.0.70/include/instance/pm.h | 59 - .../SAMD51_DFP/1.0.70/include/instance/port.h | 184 - .../SAMD51_DFP/1.0.70/include/instance/pukcc.h | 57 - .../SAMD51_DFP/1.0.70/include/instance/qspi.h | 72 - .../SAMD51_DFP/1.0.70/include/instance/ramecc.h | 54 - .../SAMD51_DFP/1.0.70/include/instance/rstc.h | 48 - .../atmel/SAMD51_DFP/1.0.70/include/instance/rtc.h | 156 - .../SAMD51_DFP/1.0.70/include/instance/sdhc0.h | 147 - .../SAMD51_DFP/1.0.70/include/instance/sdhc1.h | 147 - .../SAMD51_DFP/1.0.70/include/instance/sercom0.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom1.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom2.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom3.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom4.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom5.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom6.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/sercom7.h | 181 - .../SAMD51_DFP/1.0.70/include/instance/supc.h | 64 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tal.h | 541 -- .../atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc1.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc2.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc3.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc4.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc5.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc6.h | 109 - .../atmel/SAMD51_DFP/1.0.70/include/instance/tc7.h | 109 - .../SAMD51_DFP/1.0.70/include/instance/tcc0.h | 125 - .../SAMD51_DFP/1.0.70/include/instance/tcc1.h | 115 - .../SAMD51_DFP/1.0.70/include/instance/tcc2.h | 106 - .../SAMD51_DFP/1.0.70/include/instance/tcc3.h | 99 - .../SAMD51_DFP/1.0.70/include/instance/tcc4.h | 99 - .../SAMD51_DFP/1.0.70/include/instance/trng.h | 51 - .../atmel/SAMD51_DFP/1.0.70/include/instance/usb.h | 343 - .../atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h | 55 - .../SAMD51_DFP/1.0.70/include/pio/samd51j18a.h | 1863 ----- .../packs/atmel/SAMD51_DFP/1.0.70/include/sam.h | 54 - .../packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h | 60 - .../atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h | 1079 --- .../SAMD51_DFP/1.0.70/include/system_samd51.h | 48 - lib/python/qmk/info.py | 3 - 111 files changed, 54384 deletions(-) delete mode 100644 lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h delete mode 100644 lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h delete mode 100644 lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h delete mode 100644 lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h delete mode 100644 lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/eic.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/evsys.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/freqm.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/gclk.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/hmatrixb.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/i2s.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/icm.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/mclk.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/nvmctrl.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/osc32kctrl.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/oscctrl.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pac.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pcc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pdec.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pm.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/port.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/qspi.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ramecc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rstc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rtc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sercom.h delete mode 100644 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lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h delete mode 100644 lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h (limited to 'lib') diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h deleted file mode 100644 index 4be7e8c848..0000000000 --- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7226 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_math.h - * Description: Public header file for CMSIS DSP Library - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library - * on ARMv8M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if (x > 0) - { - posMax = (posMax - 1); - - if (x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if (x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#if 0 - /* - * @brief C custom defined PKHBT for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( - uint32_t x, - uint32_t y, - uint32_t leftshift) - { - return ( ((x ) & 0x0000FFFFUL) | - ((y << leftshift) & 0xFFFF0000UL) ); - } - - /* - * @brief C custom defined PKHTB for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( - uint32_t x, - uint32_t y, - uint32_t rightshift) - { - return ( ((x ) & 0xFFFF0000UL) | - ((y >> rightshift) & 0x0000FFFFUL) ); - } -#endif - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 8b989f851a..0000000000 --- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,223 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * ARM Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * ARM Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - - #include - - #ifndef __NO_RETURN - #define __NO_RETURN __noreturn - #endif - #ifndef __USED - #define __USED __root - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __UNALIGNED_UINT32 - __packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct - #endif - - -/* - * TI ARM Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __UNALIGNED_UINT32 - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __UNALIGNED_UINT32 - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __UNALIGNED_UINT32 - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 074cd7ab32..0000000000 --- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1899 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.1 - * @date 02. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpacked" -#pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; -#pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h deleted file mode 100644 index 2da78d3983..0000000000 --- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2103 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt b/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt deleted file mode 100644 index 8dada3edaf..0000000000 --- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld deleted file mode 100644 index 1c63547863..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD51J18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ -/*rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000*/ - rom (rx) : ORIGIN = 0x00004000, LENGTH = 0x0003C000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000; - -/* The heap size used by the application. */ -HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x800; - -_srom = ORIGIN(rom); -_lrom = LENGTH(rom); -_erom = ORIGIN(rom) + LENGTH(rom); -_sram = ORIGIN(ram); -_lram = LENGTH(ram); -_eram = ORIGIN(ram) + LENGTH(ram); - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* .heap section for syscalls */ - .heap (NOLOAD) : - { - . = ALIGN(4); - _end = .; - end = .; - _heap_start = .; - . = . + HEAP_SIZE; - _heap_end = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h deleted file mode 100644 index 80801fc128..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 0 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION -// is at least 8 digits long. -// -#define COMPONENT_VERSION 00010000 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 70 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.0" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2017-08-09 09:59:41" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h deleted file mode 100644 index 24623d00ac..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h +++ /dev/null @@ -1,598 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AC_COMPONENT_ -#define _SAMD51_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AC Analog Comparators */ -/*@{*/ - -#define AC_U2501 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ - -/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ - uint16_t :14; /*!< bit: 2..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} AC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ -#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ - -#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ -#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) -#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ - __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h deleted file mode 100644 index 33c38ae3f8..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h +++ /dev/null @@ -1,871 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ADC_COMPONENT_ -#define _SAMD51_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2500 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t :1; /*!< bit: 2 Reserved */ - uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ - uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :4; /*!< bit: 11..14 Reserved */ - uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ -#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ -#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ -#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ -#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ -#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) -#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :2; /*!< bit: 5.. 6 Reserved */ - uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :2; /*!< bit: 13..14 Reserved */ - uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ -#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ -#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ -#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ -#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ -#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) -#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ -#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) -#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ -#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) -#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ - uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ - uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ - uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ - uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ - uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ - uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ - uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ - uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) -#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ -#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ -#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ - -#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ -#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) -#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ - -/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ -#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ - -#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ -#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) -#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ -#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) -#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ -#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) -#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ -#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) -#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ -#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) -#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ -#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) -#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ -#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) -#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ -#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) -#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ -#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) -#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ -#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) -#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ - -/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQSTAT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ -#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ - -#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ -#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) -#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ -#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) -#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ -#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) -#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ -#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) -#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ -#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) -#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ -#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) -#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ -#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) -#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ -#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) -#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ -#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) -#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ -#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) -#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ -#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ - -#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ -#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) -#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ -#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) -#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ - RoReg8 Reserved1[0x1]; - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x17]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ - __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ - __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ - __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ - RoReg8 Reserved3[0x2]; - __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ - RoReg8 Reserved4[0x2]; - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h deleted file mode 100644 index 5a74eac28b..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h +++ /dev/null @@ -1,375 +0,0 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AES_COMPONENT_ -#define _SAMD51_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x220 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ - uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ - uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ - uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ -#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ -#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ -#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ -#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ -#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ -#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ -#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ -#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ -#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ -#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ -#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ -#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ -#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ -#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h deleted file mode 100644 index 9d6754998c..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h +++ /dev/null @@ -1,3207 +0,0 @@ -/** - * \file - * - * \brief Component description for CAN - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CAN_COMPONENT_ -#define _SAMD51_CAN_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CAN */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CAN Control Area Network */ -/*@{*/ - -#define CAN_U2003 -#define REV_CAN 0x321 - -/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :20; /*!< bit: 0..19 Reserved */ - uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ - uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ - uint32_t REL:4; /*!< bit: 28..31 Core Release */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CREL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ -#define CAN_CREL_RESETVALUE 0x32100000u /**< \brief (CAN_CREL reset_value) Core Release */ - -#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ -#define CAN_CREL_SUBSTEP_Msk (0xFu << CAN_CREL_SUBSTEP_Pos) -#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) -#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ -#define CAN_CREL_STEP_Msk (0xFu << CAN_CREL_STEP_Pos) -#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) -#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ -#define CAN_CREL_REL_Msk (0xFu << CAN_CREL_REL_Pos) -#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) -#define CAN_CREL_MASK 0xFFF00000u /**< \brief (CAN_CREL) MASK Register */ - -/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ENDN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ -#define CAN_ENDN_RESETVALUE 0x87654321u /**< \brief (CAN_ENDN reset_value) Endian */ - -#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ -#define CAN_ENDN_ETV_Msk (0xFFFFFFFFu << CAN_ENDN_ETV_Pos) -#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) -#define CAN_ENDN_MASK 0xFFFFFFFFu /**< \brief (CAN_ENDN) MASK Register */ - -/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_MRCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ -#define CAN_MRCFG_RESETVALUE 0x00000002u /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ - -#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ -#define CAN_MRCFG_QOS_Msk (0x3u << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) -#define CAN_MRCFG_QOS_DISABLE_Val 0x0u /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ -#define CAN_MRCFG_QOS_LOW_Val 0x1u /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ -#define CAN_MRCFG_QOS_MEDIUM_Val 0x2u /**< \brief (CAN_MRCFG) Sensitive Latency */ -#define CAN_MRCFG_QOS_HIGH_Val 0x3u /**< \brief (CAN_MRCFG) Critical Latency */ -#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_MASK 0x00000003u /**< \brief (CAN_MRCFG) MASK Register */ - -/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ - uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ - uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ - uint32_t :2; /*!< bit: 21..22 Reserved */ - uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_DBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ -#define CAN_DBTP_RESETVALUE 0x00000A33u /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ - -#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ -#define CAN_DBTP_DSJW_Msk (0xFu << CAN_DBTP_DSJW_Pos) -#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) -#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ -#define CAN_DBTP_DTSEG2_Msk (0xFu << CAN_DBTP_DTSEG2_Pos) -#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) -#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ -#define CAN_DBTP_DTSEG1_Msk (0x1Fu << CAN_DBTP_DTSEG1_Pos) -#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) -#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ -#define CAN_DBTP_DBRP_Msk (0x1Fu << CAN_DBTP_DBRP_Pos) -#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) -#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ -#define CAN_DBTP_TDC (0x1u << CAN_DBTP_TDC_Pos) -#define CAN_DBTP_MASK 0x009F1FFFu /**< \brief (CAN_DBTP) MASK Register */ - -/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ - uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ - uint32_t RX:1; /*!< bit: 7 Receive Pin */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TEST_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ -#define CAN_TEST_RESETVALUE 0x00000000u /**< \brief (CAN_TEST reset_value) Test */ - -#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ -#define CAN_TEST_LBCK (0x1u << CAN_TEST_LBCK_Pos) -#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ -#define CAN_TEST_TX_Msk (0x3u << CAN_TEST_TX_Pos) -#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) -#define CAN_TEST_TX_CORE_Val 0x0u /**< \brief (CAN_TEST) TX controlled by CAN core */ -#define CAN_TEST_TX_SAMPLE_Val 0x1u /**< \brief (CAN_TEST) TX monitoring sample point */ -#define CAN_TEST_TX_DOMINANT_Val 0x2u /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ -#define CAN_TEST_TX_RECESSIVE_Val 0x3u /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ -#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ -#define CAN_TEST_RX (0x1u << CAN_TEST_RX_Pos) -#define CAN_TEST_MASK 0x000000F0u /**< \brief (CAN_TEST) MASK Register */ - -/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ - uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RWD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ -#define CAN_RWD_RESETVALUE 0x00000000u /**< \brief (CAN_RWD reset_value) RAM Watchdog */ - -#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ -#define CAN_RWD_WDC_Msk (0xFFu << CAN_RWD_WDC_Pos) -#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) -#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ -#define CAN_RWD_WDV_Msk (0xFFu << CAN_RWD_WDV_Pos) -#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) -#define CAN_RWD_MASK 0x0000FFFFu /**< \brief (CAN_RWD) MASK Register */ - -/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INIT:1; /*!< bit: 0 Initialization */ - uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ - uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ - uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ - uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ - uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ - uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ - uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ - uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ - uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ - uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ - uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ - uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CCCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ -#define CAN_CCCR_RESETVALUE 0x00000001u /**< \brief (CAN_CCCR reset_value) CC Control */ - -#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ -#define CAN_CCCR_INIT (0x1u << CAN_CCCR_INIT_Pos) -#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ -#define CAN_CCCR_CCE (0x1u << CAN_CCCR_CCE_Pos) -#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ -#define CAN_CCCR_ASM (0x1u << CAN_CCCR_ASM_Pos) -#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ -#define CAN_CCCR_CSA (0x1u << CAN_CCCR_CSA_Pos) -#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ -#define CAN_CCCR_CSR (0x1u << CAN_CCCR_CSR_Pos) -#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ -#define CAN_CCCR_MON (0x1u << CAN_CCCR_MON_Pos) -#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ -#define CAN_CCCR_DAR (0x1u << CAN_CCCR_DAR_Pos) -#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ -#define CAN_CCCR_TEST (0x1u << CAN_CCCR_TEST_Pos) -#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ -#define CAN_CCCR_FDOE (0x1u << CAN_CCCR_FDOE_Pos) -#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ -#define CAN_CCCR_BRSE (0x1u << CAN_CCCR_BRSE_Pos) -#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ -#define CAN_CCCR_PXHD (0x1u << CAN_CCCR_PXHD_Pos) -#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ -#define CAN_CCCR_EFBI (0x1u << CAN_CCCR_EFBI_Pos) -#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ -#define CAN_CCCR_TXP (0x1u << CAN_CCCR_TXP_Pos) -#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ -#define CAN_CCCR_NISO (0x1u << CAN_CCCR_NISO_Pos) -#define CAN_CCCR_MASK 0x0000F3FFu /**< \brief (CAN_CCCR) MASK Register */ - -/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ - uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ - uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ -#define CAN_NBTP_RESETVALUE 0x06000A03u /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ - -#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ -#define CAN_NBTP_NTSEG2_Msk (0x7Fu << CAN_NBTP_NTSEG2_Pos) -#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) -#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ -#define CAN_NBTP_NTSEG1_Msk (0xFFu << CAN_NBTP_NTSEG1_Pos) -#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) -#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ -#define CAN_NBTP_NBRP_Msk (0x1FFu << CAN_NBTP_NBRP_Pos) -#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) -#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ -#define CAN_NBTP_NSJW_Msk (0x7Fu << CAN_NBTP_NSJW_Pos) -#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) -#define CAN_NBTP_MASK 0xFFFFFF7Fu /**< \brief (CAN_NBTP) MASK Register */ - -/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ - uint32_t :14; /*!< bit: 2..15 Reserved */ - uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ -#define CAN_TSCC_RESETVALUE 0x00000000u /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ - -#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ -#define CAN_TSCC_TSS_Msk (0x3u << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) -#define CAN_TSCC_TSS_ZERO_Val 0x0u /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ -#define CAN_TSCC_TSS_INC_Val 0x1u /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ -#define CAN_TSCC_TSS_EXT_Val 0x2u /**< \brief (CAN_TSCC) External timestamp counter value used */ -#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ -#define CAN_TSCC_TCP_Msk (0xFu << CAN_TSCC_TCP_Pos) -#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) -#define CAN_TSCC_MASK 0x000F0003u /**< \brief (CAN_TSCC) MASK Register */ - -/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ -#define CAN_TSCV_RESETVALUE 0x00000000u /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ - -#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ -#define CAN_TSCV_TSC_Msk (0xFFFFu << CAN_TSCV_TSC_Pos) -#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) -#define CAN_TSCV_MASK 0x0000FFFFu /**< \brief (CAN_TSCV) MASK Register */ - -/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ - uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ -#define CAN_TOCC_RESETVALUE 0xFFFF0000u /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ - -#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ -#define CAN_TOCC_ETOC (0x1u << CAN_TOCC_ETOC_Pos) -#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ -#define CAN_TOCC_TOS_Msk (0x3u << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) -#define CAN_TOCC_TOS_CONT_Val 0x0u /**< \brief (CAN_TOCC) Continuout operation */ -#define CAN_TOCC_TOS_TXEF_Val 0x1u /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ -#define CAN_TOCC_TOS_RXF0_Val 0x2u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ -#define CAN_TOCC_TOS_RXF1_Val 0x3u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ -#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ -#define CAN_TOCC_TOP_Msk (0xFFFFu << CAN_TOCC_TOP_Pos) -#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) -#define CAN_TOCC_MASK 0xFFFF0007u /**< \brief (CAN_TOCC) MASK Register */ - -/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ -#define CAN_TOCV_RESETVALUE 0x0000FFFFu /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ - -#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ -#define CAN_TOCV_TOC_Msk (0xFFFFu << CAN_TOCV_TOC_Pos) -#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) -#define CAN_TOCV_MASK 0x0000FFFFu /**< \brief (CAN_TOCV) MASK Register */ - -/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ - uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ - uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ - uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ECR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ -#define CAN_ECR_RESETVALUE 0x00000000u /**< \brief (CAN_ECR reset_value) Error Counter */ - -#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ -#define CAN_ECR_TEC_Msk (0xFFu << CAN_ECR_TEC_Pos) -#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) -#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ -#define CAN_ECR_REC_Msk (0x7Fu << CAN_ECR_REC_Pos) -#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) -#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ -#define CAN_ECR_RP (0x1u << CAN_ECR_RP_Pos) -#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ -#define CAN_ECR_CEL_Msk (0xFFu << CAN_ECR_CEL_Pos) -#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) -#define CAN_ECR_MASK 0x00FFFFFFu /**< \brief (CAN_ECR) MASK Register */ - -/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ - uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ - uint32_t EP:1; /*!< bit: 5 Error Passive */ - uint32_t EW:1; /*!< bit: 6 Warning Status */ - uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ - uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ - uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ - uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ - uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ - uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_PSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ -#define CAN_PSR_RESETVALUE 0x00000707u /**< \brief (CAN_PSR reset_value) Protocol Status */ - -#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ -#define CAN_PSR_LEC_Msk (0x7u << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) -#define CAN_PSR_LEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_LEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_LEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_LEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_LEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_LEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_LEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_LEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ -#define CAN_PSR_ACT_Msk (0x3u << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) -#define CAN_PSR_ACT_SYNC_Val 0x0u /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ -#define CAN_PSR_ACT_IDLE_Val 0x1u /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ -#define CAN_PSR_ACT_RX_Val 0x2u /**< \brief (CAN_PSR) Node is operating as receiver */ -#define CAN_PSR_ACT_TX_Val 0x3u /**< \brief (CAN_PSR) Node is operating as transmitter */ -#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ -#define CAN_PSR_EP (0x1u << CAN_PSR_EP_Pos) -#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ -#define CAN_PSR_EW (0x1u << CAN_PSR_EW_Pos) -#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ -#define CAN_PSR_BO (0x1u << CAN_PSR_BO_Pos) -#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ -#define CAN_PSR_DLEC_Msk (0x7u << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) -#define CAN_PSR_DLEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_DLEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_DLEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_DLEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_DLEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_DLEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_DLEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_DLEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ -#define CAN_PSR_RESI (0x1u << CAN_PSR_RESI_Pos) -#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ -#define CAN_PSR_RBRS (0x1u << CAN_PSR_RBRS_Pos) -#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ -#define CAN_PSR_RFDF (0x1u << CAN_PSR_RFDF_Pos) -#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ -#define CAN_PSR_PXE (0x1u << CAN_PSR_PXE_Pos) -#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ -#define CAN_PSR_TDCV_Msk (0x7Fu << CAN_PSR_TDCV_Pos) -#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) -#define CAN_PSR_MASK 0x007F7FFFu /**< \brief (CAN_PSR) MASK Register */ - -/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TDCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ -#define CAN_TDCR_RESETVALUE 0x00000000u /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ - -#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ -#define CAN_TDCR_TDCF_Msk (0x7Fu << CAN_TDCR_TDCF_Pos) -#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) -#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ -#define CAN_TDCR_TDCO_Msk (0x7Fu << CAN_TDCR_TDCO_Pos) -#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) -#define CAN_TDCR_MASK 0x00007F7Fu /**< \brief (CAN_TDCR) MASK Register */ - -/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ - uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ - uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ - uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ - uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ - uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ - uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ - uint32_t HPM:1; /*!< bit: 8 High Priority Message */ - uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ - uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ - uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ - uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ - uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ - uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ - uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ - uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ - uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ - uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ - uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ - uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ - uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ - uint32_t EP:1; /*!< bit: 23 Error Passive */ - uint32_t EW:1; /*!< bit: 24 Warning Status */ - uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ - uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ - uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ - uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ - uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ -#define CAN_IR_RESETVALUE 0x00000000u /**< \brief (CAN_IR reset_value) Interrupt */ - -#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ -#define CAN_IR_RF0N (0x1u << CAN_IR_RF0N_Pos) -#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ -#define CAN_IR_RF0W (0x1u << CAN_IR_RF0W_Pos) -#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ -#define CAN_IR_RF0F (0x1u << CAN_IR_RF0F_Pos) -#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ -#define CAN_IR_RF0L (0x1u << CAN_IR_RF0L_Pos) -#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ -#define CAN_IR_RF1N (0x1u << CAN_IR_RF1N_Pos) -#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ -#define CAN_IR_RF1W (0x1u << CAN_IR_RF1W_Pos) -#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ -#define CAN_IR_RF1F (0x1u << CAN_IR_RF1F_Pos) -#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ -#define CAN_IR_RF1L (0x1u << CAN_IR_RF1L_Pos) -#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ -#define CAN_IR_HPM (0x1u << CAN_IR_HPM_Pos) -#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ -#define CAN_IR_TC (0x1u << CAN_IR_TC_Pos) -#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ -#define CAN_IR_TCF (0x1u << CAN_IR_TCF_Pos) -#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ -#define CAN_IR_TFE (0x1u << CAN_IR_TFE_Pos) -#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ -#define CAN_IR_TEFN (0x1u << CAN_IR_TEFN_Pos) -#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ -#define CAN_IR_TEFW (0x1u << CAN_IR_TEFW_Pos) -#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ -#define CAN_IR_TEFF (0x1u << CAN_IR_TEFF_Pos) -#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ -#define CAN_IR_TEFL (0x1u << CAN_IR_TEFL_Pos) -#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ -#define CAN_IR_TSW (0x1u << CAN_IR_TSW_Pos) -#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ -#define CAN_IR_MRAF (0x1u << CAN_IR_MRAF_Pos) -#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ -#define CAN_IR_TOO (0x1u << CAN_IR_TOO_Pos) -#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ -#define CAN_IR_DRX (0x1u << CAN_IR_DRX_Pos) -#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ -#define CAN_IR_BEC (0x1u << CAN_IR_BEC_Pos) -#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ -#define CAN_IR_BEU (0x1u << CAN_IR_BEU_Pos) -#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ -#define CAN_IR_ELO (0x1u << CAN_IR_ELO_Pos) -#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ -#define CAN_IR_EP (0x1u << CAN_IR_EP_Pos) -#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ -#define CAN_IR_EW (0x1u << CAN_IR_EW_Pos) -#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ -#define CAN_IR_BO (0x1u << CAN_IR_BO_Pos) -#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ -#define CAN_IR_WDI (0x1u << CAN_IR_WDI_Pos) -#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ -#define CAN_IR_PEA (0x1u << CAN_IR_PEA_Pos) -#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ -#define CAN_IR_PED (0x1u << CAN_IR_PED_Pos) -#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ -#define CAN_IR_ARA (0x1u << CAN_IR_ARA_Pos) -#define CAN_IR_MASK 0x3FFFFFFFu /**< \brief (CAN_IR) MASK Register */ - -/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ - uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ - uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ - uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ - uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ - uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ - uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ - uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ - uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ - uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ - uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ - uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ - uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ - uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ - uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ - uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ - uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ - uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ - uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ - uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ - uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ - uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ - uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ - uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ - uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ - uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ - uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ - uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ - uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ - uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ -#define CAN_IE_RESETVALUE 0x00000000u /**< \brief (CAN_IE reset_value) Interrupt Enable */ - -#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ -#define CAN_IE_RF0NE (0x1u << CAN_IE_RF0NE_Pos) -#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF0WE (0x1u << CAN_IE_RF0WE_Pos) -#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ -#define CAN_IE_RF0FE (0x1u << CAN_IE_RF0FE_Pos) -#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ -#define CAN_IE_RF0LE (0x1u << CAN_IE_RF0LE_Pos) -#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ -#define CAN_IE_RF1NE (0x1u << CAN_IE_RF1NE_Pos) -#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF1WE (0x1u << CAN_IE_RF1WE_Pos) -#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ -#define CAN_IE_RF1FE (0x1u << CAN_IE_RF1FE_Pos) -#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ -#define CAN_IE_RF1LE (0x1u << CAN_IE_RF1LE_Pos) -#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ -#define CAN_IE_HPME (0x1u << CAN_IE_HPME_Pos) -#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ -#define CAN_IE_TCE (0x1u << CAN_IE_TCE_Pos) -#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ -#define CAN_IE_TCFE (0x1u << CAN_IE_TCFE_Pos) -#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ -#define CAN_IE_TFEE (0x1u << CAN_IE_TFEE_Pos) -#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ -#define CAN_IE_TEFNE (0x1u << CAN_IE_TEFNE_Pos) -#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ -#define CAN_IE_TEFWE (0x1u << CAN_IE_TEFWE_Pos) -#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ -#define CAN_IE_TEFFE (0x1u << CAN_IE_TEFFE_Pos) -#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ -#define CAN_IE_TEFLE (0x1u << CAN_IE_TEFLE_Pos) -#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ -#define CAN_IE_TSWE (0x1u << CAN_IE_TSWE_Pos) -#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ -#define CAN_IE_MRAFE (0x1u << CAN_IE_MRAFE_Pos) -#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ -#define CAN_IE_TOOE (0x1u << CAN_IE_TOOE_Pos) -#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ -#define CAN_IE_DRXE (0x1u << CAN_IE_DRXE_Pos) -#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ -#define CAN_IE_BECE (0x1u << CAN_IE_BECE_Pos) -#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ -#define CAN_IE_BEUE (0x1u << CAN_IE_BEUE_Pos) -#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ -#define CAN_IE_ELOE (0x1u << CAN_IE_ELOE_Pos) -#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ -#define CAN_IE_EPE (0x1u << CAN_IE_EPE_Pos) -#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ -#define CAN_IE_EWE (0x1u << CAN_IE_EWE_Pos) -#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ -#define CAN_IE_BOE (0x1u << CAN_IE_BOE_Pos) -#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ -#define CAN_IE_WDIE (0x1u << CAN_IE_WDIE_Pos) -#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ -#define CAN_IE_PEAE (0x1u << CAN_IE_PEAE_Pos) -#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ -#define CAN_IE_PEDE (0x1u << CAN_IE_PEDE_Pos) -#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ -#define CAN_IE_ARAE (0x1u << CAN_IE_ARAE_Pos) -#define CAN_IE_MASK 0x3FFFFFFFu /**< \brief (CAN_IE) MASK Register */ - -/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ - uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ - uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ - uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ - uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ - uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ - uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ - uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ - uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ - uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ - uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ - uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ - uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ - uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ - uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ - uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ - uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ - uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ - uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ - uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ - uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ - uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ - uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ - uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ - uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ - uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ - uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ - uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ - uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ - uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ -#define CAN_ILS_RESETVALUE 0x00000000u /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ - -#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ -#define CAN_ILS_RF0NL (0x1u << CAN_ILS_RF0NL_Pos) -#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF0WL (0x1u << CAN_ILS_RF0WL_Pos) -#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ -#define CAN_ILS_RF0FL (0x1u << CAN_ILS_RF0FL_Pos) -#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ -#define CAN_ILS_RF0LL (0x1u << CAN_ILS_RF0LL_Pos) -#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ -#define CAN_ILS_RF1NL (0x1u << CAN_ILS_RF1NL_Pos) -#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF1WL (0x1u << CAN_ILS_RF1WL_Pos) -#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ -#define CAN_ILS_RF1FL (0x1u << CAN_ILS_RF1FL_Pos) -#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ -#define CAN_ILS_RF1LL (0x1u << CAN_ILS_RF1LL_Pos) -#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ -#define CAN_ILS_HPML (0x1u << CAN_ILS_HPML_Pos) -#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ -#define CAN_ILS_TCL (0x1u << CAN_ILS_TCL_Pos) -#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ -#define CAN_ILS_TCFL (0x1u << CAN_ILS_TCFL_Pos) -#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ -#define CAN_ILS_TFEL (0x1u << CAN_ILS_TFEL_Pos) -#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ -#define CAN_ILS_TEFNL (0x1u << CAN_ILS_TEFNL_Pos) -#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ -#define CAN_ILS_TEFWL (0x1u << CAN_ILS_TEFWL_Pos) -#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ -#define CAN_ILS_TEFFL (0x1u << CAN_ILS_TEFFL_Pos) -#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ -#define CAN_ILS_TEFLL (0x1u << CAN_ILS_TEFLL_Pos) -#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ -#define CAN_ILS_TSWL (0x1u << CAN_ILS_TSWL_Pos) -#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ -#define CAN_ILS_MRAFL (0x1u << CAN_ILS_MRAFL_Pos) -#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ -#define CAN_ILS_TOOL (0x1u << CAN_ILS_TOOL_Pos) -#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ -#define CAN_ILS_DRXL (0x1u << CAN_ILS_DRXL_Pos) -#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ -#define CAN_ILS_BECL (0x1u << CAN_ILS_BECL_Pos) -#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ -#define CAN_ILS_BEUL (0x1u << CAN_ILS_BEUL_Pos) -#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ -#define CAN_ILS_ELOL (0x1u << CAN_ILS_ELOL_Pos) -#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ -#define CAN_ILS_EPL (0x1u << CAN_ILS_EPL_Pos) -#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ -#define CAN_ILS_EWL (0x1u << CAN_ILS_EWL_Pos) -#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ -#define CAN_ILS_BOL (0x1u << CAN_ILS_BOL_Pos) -#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ -#define CAN_ILS_WDIL (0x1u << CAN_ILS_WDIL_Pos) -#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ -#define CAN_ILS_PEAL (0x1u << CAN_ILS_PEAL_Pos) -#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ -#define CAN_ILS_PEDL (0x1u << CAN_ILS_PEDL_Pos) -#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ -#define CAN_ILS_ARAL (0x1u << CAN_ILS_ARAL_Pos) -#define CAN_ILS_MASK 0x3FFFFFFFu /**< \brief (CAN_ILS) MASK Register */ - -/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ - uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ -#define CAN_ILE_RESETVALUE 0x00000000u /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ - -#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ -#define CAN_ILE_EINT0 (0x1u << CAN_ILE_EINT0_Pos) -#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ -#define CAN_ILE_EINT1 (0x1u << CAN_ILE_EINT1_Pos) -#define CAN_ILE_MASK 0x00000003u /**< \brief (CAN_ILE) MASK Register */ - -/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ - uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ - uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ - uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_GFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ -#define CAN_GFC_RESETVALUE 0x00000000u /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ - -#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ -#define CAN_GFC_RRFE (0x1u << CAN_GFC_RRFE_Pos) -#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ -#define CAN_GFC_RRFS (0x1u << CAN_GFC_RRFS_Pos) -#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ -#define CAN_GFC_ANFE_Msk (0x3u << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) -#define CAN_GFC_ANFE_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFE_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFE_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ -#define CAN_GFC_ANFS_Msk (0x3u << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) -#define CAN_GFC_ANFS_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFS_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFS_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_MASK 0x0000003Fu /**< \brief (CAN_GFC) MASK Register */ - -/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ - uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ -#define CAN_SIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ - -#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ -#define CAN_SIDFC_FLSSA_Msk (0xFFFFu << CAN_SIDFC_FLSSA_Pos) -#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) -#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ -#define CAN_SIDFC_LSS_Msk (0xFFu << CAN_SIDFC_LSS_Pos) -#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) -#define CAN_SIDFC_MASK 0x00FFFFFFu /**< \brief (CAN_SIDFC) MASK Register */ - -/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ - uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ -#define CAN_XIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ - -#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ -#define CAN_XIDFC_FLESA_Msk (0xFFFFu << CAN_XIDFC_FLESA_Pos) -#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) -#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ -#define CAN_XIDFC_LSE_Msk (0x7Fu << CAN_XIDFC_LSE_Pos) -#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) -#define CAN_XIDFC_MASK 0x007FFFFFu /**< \brief (CAN_XIDFC) MASK Register */ - -/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ - uint32_t :3; /*!< bit: 29..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ -#define CAN_XIDAM_RESETVALUE 0x1FFFFFFFu /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ - -#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ -#define CAN_XIDAM_EIDM_Msk (0x1FFFFFFFu << CAN_XIDAM_EIDM_Pos) -#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) -#define CAN_XIDAM_MASK 0x1FFFFFFFu /**< \brief (CAN_XIDAM) MASK Register */ - -/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ - uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ - uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ - uint32_t FLST:1; /*!< bit: 15 Filter List */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_HPMS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ -#define CAN_HPMS_RESETVALUE 0x00000000u /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ - -#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ -#define CAN_HPMS_BIDX_Msk (0x3Fu << CAN_HPMS_BIDX_Pos) -#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) -#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ -#define CAN_HPMS_MSI_Msk (0x3u << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) -#define CAN_HPMS_MSI_NONE_Val 0x0u /**< \brief (CAN_HPMS) No FIFO selected */ -#define CAN_HPMS_MSI_LOST_Val 0x1u /**< \brief (CAN_HPMS) FIFO message lost */ -#define CAN_HPMS_MSI_FIFO0_Val 0x2u /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ -#define CAN_HPMS_MSI_FIFO1_Val 0x3u /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ -#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ -#define CAN_HPMS_FIDX_Msk (0x7Fu << CAN_HPMS_FIDX_Pos) -#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) -#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ -#define CAN_HPMS_FLST (0x1u << CAN_HPMS_FLST_Pos) -#define CAN_HPMS_MASK 0x0000FFFFu /**< \brief (CAN_HPMS) MASK Register */ - -/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND0:1; /*!< bit: 0 New Data 0 */ - uint32_t ND1:1; /*!< bit: 1 New Data 1 */ - uint32_t ND2:1; /*!< bit: 2 New Data 2 */ - uint32_t ND3:1; /*!< bit: 3 New Data 3 */ - uint32_t ND4:1; /*!< bit: 4 New Data 4 */ - uint32_t ND5:1; /*!< bit: 5 New Data 5 */ - uint32_t ND6:1; /*!< bit: 6 New Data 6 */ - uint32_t ND7:1; /*!< bit: 7 New Data 7 */ - uint32_t ND8:1; /*!< bit: 8 New Data 8 */ - uint32_t ND9:1; /*!< bit: 9 New Data 9 */ - uint32_t ND10:1; /*!< bit: 10 New Data 10 */ - uint32_t ND11:1; /*!< bit: 11 New Data 11 */ - uint32_t ND12:1; /*!< bit: 12 New Data 12 */ - uint32_t ND13:1; /*!< bit: 13 New Data 13 */ - uint32_t ND14:1; /*!< bit: 14 New Data 14 */ - uint32_t ND15:1; /*!< bit: 15 New Data 15 */ - uint32_t ND16:1; /*!< bit: 16 New Data 16 */ - uint32_t ND17:1; /*!< bit: 17 New Data 17 */ - uint32_t ND18:1; /*!< bit: 18 New Data 18 */ - uint32_t ND19:1; /*!< bit: 19 New Data 19 */ - uint32_t ND20:1; /*!< bit: 20 New Data 20 */ - uint32_t ND21:1; /*!< bit: 21 New Data 21 */ - uint32_t ND22:1; /*!< bit: 22 New Data 22 */ - uint32_t ND23:1; /*!< bit: 23 New Data 23 */ - uint32_t ND24:1; /*!< bit: 24 New Data 24 */ - uint32_t ND25:1; /*!< bit: 25 New Data 25 */ - uint32_t ND26:1; /*!< bit: 26 New Data 26 */ - uint32_t ND27:1; /*!< bit: 27 New Data 27 */ - uint32_t ND28:1; /*!< bit: 28 New Data 28 */ - uint32_t ND29:1; /*!< bit: 29 New Data 29 */ - uint32_t ND30:1; /*!< bit: 30 New Data 30 */ - uint32_t ND31:1; /*!< bit: 31 New Data 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ -#define CAN_NDAT1_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ - -#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ -#define CAN_NDAT1_ND0 (0x1u << CAN_NDAT1_ND0_Pos) -#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ -#define CAN_NDAT1_ND1 (0x1u << CAN_NDAT1_ND1_Pos) -#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ -#define CAN_NDAT1_ND2 (0x1u << CAN_NDAT1_ND2_Pos) -#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ -#define CAN_NDAT1_ND3 (0x1u << CAN_NDAT1_ND3_Pos) -#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ -#define CAN_NDAT1_ND4 (0x1u << CAN_NDAT1_ND4_Pos) -#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ -#define CAN_NDAT1_ND5 (0x1u << CAN_NDAT1_ND5_Pos) -#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ -#define CAN_NDAT1_ND6 (0x1u << CAN_NDAT1_ND6_Pos) -#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ -#define CAN_NDAT1_ND7 (0x1u << CAN_NDAT1_ND7_Pos) -#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ -#define CAN_NDAT1_ND8 (0x1u << CAN_NDAT1_ND8_Pos) -#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ -#define CAN_NDAT1_ND9 (0x1u << CAN_NDAT1_ND9_Pos) -#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ -#define CAN_NDAT1_ND10 (0x1u << CAN_NDAT1_ND10_Pos) -#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ -#define CAN_NDAT1_ND11 (0x1u << CAN_NDAT1_ND11_Pos) -#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ -#define CAN_NDAT1_ND12 (0x1u << CAN_NDAT1_ND12_Pos) -#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ -#define CAN_NDAT1_ND13 (0x1u << CAN_NDAT1_ND13_Pos) -#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ -#define CAN_NDAT1_ND14 (0x1u << CAN_NDAT1_ND14_Pos) -#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ -#define CAN_NDAT1_ND15 (0x1u << CAN_NDAT1_ND15_Pos) -#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ -#define CAN_NDAT1_ND16 (0x1u << CAN_NDAT1_ND16_Pos) -#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ -#define CAN_NDAT1_ND17 (0x1u << CAN_NDAT1_ND17_Pos) -#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ -#define CAN_NDAT1_ND18 (0x1u << CAN_NDAT1_ND18_Pos) -#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ -#define CAN_NDAT1_ND19 (0x1u << CAN_NDAT1_ND19_Pos) -#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ -#define CAN_NDAT1_ND20 (0x1u << CAN_NDAT1_ND20_Pos) -#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ -#define CAN_NDAT1_ND21 (0x1u << CAN_NDAT1_ND21_Pos) -#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ -#define CAN_NDAT1_ND22 (0x1u << CAN_NDAT1_ND22_Pos) -#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ -#define CAN_NDAT1_ND23 (0x1u << CAN_NDAT1_ND23_Pos) -#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ -#define CAN_NDAT1_ND24 (0x1u << CAN_NDAT1_ND24_Pos) -#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ -#define CAN_NDAT1_ND25 (0x1u << CAN_NDAT1_ND25_Pos) -#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ -#define CAN_NDAT1_ND26 (0x1u << CAN_NDAT1_ND26_Pos) -#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ -#define CAN_NDAT1_ND27 (0x1u << CAN_NDAT1_ND27_Pos) -#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ -#define CAN_NDAT1_ND28 (0x1u << CAN_NDAT1_ND28_Pos) -#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ -#define CAN_NDAT1_ND29 (0x1u << CAN_NDAT1_ND29_Pos) -#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ -#define CAN_NDAT1_ND30 (0x1u << CAN_NDAT1_ND30_Pos) -#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ -#define CAN_NDAT1_ND31 (0x1u << CAN_NDAT1_ND31_Pos) -#define CAN_NDAT1_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT1) MASK Register */ - -/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND32:1; /*!< bit: 0 New Data 32 */ - uint32_t ND33:1; /*!< bit: 1 New Data 33 */ - uint32_t ND34:1; /*!< bit: 2 New Data 34 */ - uint32_t ND35:1; /*!< bit: 3 New Data 35 */ - uint32_t ND36:1; /*!< bit: 4 New Data 36 */ - uint32_t ND37:1; /*!< bit: 5 New Data 37 */ - uint32_t ND38:1; /*!< bit: 6 New Data 38 */ - uint32_t ND39:1; /*!< bit: 7 New Data 39 */ - uint32_t ND40:1; /*!< bit: 8 New Data 40 */ - uint32_t ND41:1; /*!< bit: 9 New Data 41 */ - uint32_t ND42:1; /*!< bit: 10 New Data 42 */ - uint32_t ND43:1; /*!< bit: 11 New Data 43 */ - uint32_t ND44:1; /*!< bit: 12 New Data 44 */ - uint32_t ND45:1; /*!< bit: 13 New Data 45 */ - uint32_t ND46:1; /*!< bit: 14 New Data 46 */ - uint32_t ND47:1; /*!< bit: 15 New Data 47 */ - uint32_t ND48:1; /*!< bit: 16 New Data 48 */ - uint32_t ND49:1; /*!< bit: 17 New Data 49 */ - uint32_t ND50:1; /*!< bit: 18 New Data 50 */ - uint32_t ND51:1; /*!< bit: 19 New Data 51 */ - uint32_t ND52:1; /*!< bit: 20 New Data 52 */ - uint32_t ND53:1; /*!< bit: 21 New Data 53 */ - uint32_t ND54:1; /*!< bit: 22 New Data 54 */ - uint32_t ND55:1; /*!< bit: 23 New Data 55 */ - uint32_t ND56:1; /*!< bit: 24 New Data 56 */ - uint32_t ND57:1; /*!< bit: 25 New Data 57 */ - uint32_t ND58:1; /*!< bit: 26 New Data 58 */ - uint32_t ND59:1; /*!< bit: 27 New Data 59 */ - uint32_t ND60:1; /*!< bit: 28 New Data 60 */ - uint32_t ND61:1; /*!< bit: 29 New Data 61 */ - uint32_t ND62:1; /*!< bit: 30 New Data 62 */ - uint32_t ND63:1; /*!< bit: 31 New Data 63 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ -#define CAN_NDAT2_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ - -#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ -#define CAN_NDAT2_ND32 (0x1u << CAN_NDAT2_ND32_Pos) -#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ -#define CAN_NDAT2_ND33 (0x1u << CAN_NDAT2_ND33_Pos) -#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ -#define CAN_NDAT2_ND34 (0x1u << CAN_NDAT2_ND34_Pos) -#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ -#define CAN_NDAT2_ND35 (0x1u << CAN_NDAT2_ND35_Pos) -#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ -#define CAN_NDAT2_ND36 (0x1u << CAN_NDAT2_ND36_Pos) -#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ -#define CAN_NDAT2_ND37 (0x1u << CAN_NDAT2_ND37_Pos) -#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ -#define CAN_NDAT2_ND38 (0x1u << CAN_NDAT2_ND38_Pos) -#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ -#define CAN_NDAT2_ND39 (0x1u << CAN_NDAT2_ND39_Pos) -#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ -#define CAN_NDAT2_ND40 (0x1u << CAN_NDAT2_ND40_Pos) -#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ -#define CAN_NDAT2_ND41 (0x1u << CAN_NDAT2_ND41_Pos) -#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ -#define CAN_NDAT2_ND42 (0x1u << CAN_NDAT2_ND42_Pos) -#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ -#define CAN_NDAT2_ND43 (0x1u << CAN_NDAT2_ND43_Pos) -#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ -#define CAN_NDAT2_ND44 (0x1u << CAN_NDAT2_ND44_Pos) -#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ -#define CAN_NDAT2_ND45 (0x1u << CAN_NDAT2_ND45_Pos) -#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ -#define CAN_NDAT2_ND46 (0x1u << CAN_NDAT2_ND46_Pos) -#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ -#define CAN_NDAT2_ND47 (0x1u << CAN_NDAT2_ND47_Pos) -#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ -#define CAN_NDAT2_ND48 (0x1u << CAN_NDAT2_ND48_Pos) -#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ -#define CAN_NDAT2_ND49 (0x1u << CAN_NDAT2_ND49_Pos) -#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ -#define CAN_NDAT2_ND50 (0x1u << CAN_NDAT2_ND50_Pos) -#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ -#define CAN_NDAT2_ND51 (0x1u << CAN_NDAT2_ND51_Pos) -#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ -#define CAN_NDAT2_ND52 (0x1u << CAN_NDAT2_ND52_Pos) -#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ -#define CAN_NDAT2_ND53 (0x1u << CAN_NDAT2_ND53_Pos) -#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ -#define CAN_NDAT2_ND54 (0x1u << CAN_NDAT2_ND54_Pos) -#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ -#define CAN_NDAT2_ND55 (0x1u << CAN_NDAT2_ND55_Pos) -#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ -#define CAN_NDAT2_ND56 (0x1u << CAN_NDAT2_ND56_Pos) -#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ -#define CAN_NDAT2_ND57 (0x1u << CAN_NDAT2_ND57_Pos) -#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ -#define CAN_NDAT2_ND58 (0x1u << CAN_NDAT2_ND58_Pos) -#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ -#define CAN_NDAT2_ND59 (0x1u << CAN_NDAT2_ND59_Pos) -#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ -#define CAN_NDAT2_ND60 (0x1u << CAN_NDAT2_ND60_Pos) -#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ -#define CAN_NDAT2_ND61 (0x1u << CAN_NDAT2_ND61_Pos) -#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ -#define CAN_NDAT2_ND62 (0x1u << CAN_NDAT2_ND62_Pos) -#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ -#define CAN_NDAT2_ND63 (0x1u << CAN_NDAT2_ND63_Pos) -#define CAN_NDAT2_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT2) MASK Register */ - -/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ - uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ - uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ -#define CAN_RXF0C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ - -#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ -#define CAN_RXF0C_F0SA_Msk (0xFFFFu << CAN_RXF0C_F0SA_Pos) -#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) -#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ -#define CAN_RXF0C_F0S_Msk (0x7Fu << CAN_RXF0C_F0S_Pos) -#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) -#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ -#define CAN_RXF0C_F0WM_Msk (0x7Fu << CAN_RXF0C_F0WM_Pos) -#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) -#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ -#define CAN_RXF0C_F0OM (0x1u << CAN_RXF0C_F0OM_Pos) -#define CAN_RXF0C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF0C) MASK Register */ - -/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ -#define CAN_RXF0S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ - -#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ -#define CAN_RXF0S_F0FL_Msk (0x7Fu << CAN_RXF0S_F0FL_Pos) -#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) -#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ -#define CAN_RXF0S_F0GI_Msk (0x3Fu << CAN_RXF0S_F0GI_Pos) -#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) -#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ -#define CAN_RXF0S_F0PI_Msk (0x3Fu << CAN_RXF0S_F0PI_Pos) -#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) -#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ -#define CAN_RXF0S_F0F (0x1u << CAN_RXF0S_F0F_Pos) -#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ -#define CAN_RXF0S_RF0L (0x1u << CAN_RXF0S_RF0L_Pos) -#define CAN_RXF0S_MASK 0x033F3F7Fu /**< \brief (CAN_RXF0S) MASK Register */ - -/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ -#define CAN_RXF0A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ - -#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ -#define CAN_RXF0A_F0AI_Msk (0x3Fu << CAN_RXF0A_F0AI_Pos) -#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) -#define CAN_RXF0A_MASK 0x0000003Fu /**< \brief (CAN_RXF0A) MASK Register */ - -/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ -#define CAN_RXBC_RESETVALUE 0x00000000u /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ - -#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ -#define CAN_RXBC_RBSA_Msk (0xFFFFu << CAN_RXBC_RBSA_Pos) -#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) -#define CAN_RXBC_MASK 0x0000FFFFu /**< \brief (CAN_RXBC) MASK Register */ - -/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ - uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ - uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ -#define CAN_RXF1C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ - -#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ -#define CAN_RXF1C_F1SA_Msk (0xFFFFu << CAN_RXF1C_F1SA_Pos) -#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) -#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ -#define CAN_RXF1C_F1S_Msk (0x7Fu << CAN_RXF1C_F1S_Pos) -#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) -#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ -#define CAN_RXF1C_F1WM_Msk (0x7Fu << CAN_RXF1C_F1WM_Pos) -#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) -#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ -#define CAN_RXF1C_F1OM (0x1u << CAN_RXF1C_F1OM_Pos) -#define CAN_RXF1C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF1C) MASK Register */ - -/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ - uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ - uint32_t :4; /*!< bit: 26..29 Reserved */ - uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ -#define CAN_RXF1S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ - -#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ -#define CAN_RXF1S_F1FL_Msk (0x7Fu << CAN_RXF1S_F1FL_Pos) -#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) -#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ -#define CAN_RXF1S_F1GI_Msk (0x3Fu << CAN_RXF1S_F1GI_Pos) -#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) -#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ -#define CAN_RXF1S_F1PI_Msk (0x3Fu << CAN_RXF1S_F1PI_Pos) -#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) -#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ -#define CAN_RXF1S_F1F (0x1u << CAN_RXF1S_F1F_Pos) -#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ -#define CAN_RXF1S_RF1L (0x1u << CAN_RXF1S_RF1L_Pos) -#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ -#define CAN_RXF1S_DMS_Msk (0x3u << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) -#define CAN_RXF1S_DMS_IDLE_Val 0x0u /**< \brief (CAN_RXF1S) Idle state */ -#define CAN_RXF1S_DMS_DBGA_Val 0x1u /**< \brief (CAN_RXF1S) Debug message A received */ -#define CAN_RXF1S_DMS_DBGB_Val 0x2u /**< \brief (CAN_RXF1S) Debug message A/B received */ -#define CAN_RXF1S_DMS_DBGC_Val 0x3u /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ -#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_MASK 0xC33F3F7Fu /**< \brief (CAN_RXF1S) MASK Register */ - -/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ -#define CAN_RXF1A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ - -#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ -#define CAN_RXF1A_F1AI_Msk (0x3Fu << CAN_RXF1A_F1AI_Pos) -#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) -#define CAN_RXF1A_MASK 0x0000003Fu /**< \brief (CAN_RXF1A) MASK Register */ - -/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ -#define CAN_RXESC_RESETVALUE 0x00000000u /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ - -#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ -#define CAN_RXESC_F0DS_Msk (0x7u << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) -#define CAN_RXESC_F0DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F0DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F0DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F0DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F0DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F0DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F0DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F0DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ -#define CAN_RXESC_F1DS_Msk (0x7u << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) -#define CAN_RXESC_F1DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F1DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F1DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F1DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F1DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F1DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F1DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F1DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ -#define CAN_RXESC_RBDS_Msk (0x7u << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) -#define CAN_RXESC_RBDS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_RBDS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_RBDS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_RBDS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_RBDS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_RBDS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_RBDS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_RBDS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_MASK 0x00000777u /**< \brief (CAN_RXESC) MASK Register */ - -/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ - uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ - uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ -#define CAN_TXBC_RESETVALUE 0x00000000u /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ - -#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ -#define CAN_TXBC_TBSA_Msk (0xFFFFu << CAN_TXBC_TBSA_Pos) -#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) -#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ -#define CAN_TXBC_NDTB_Msk (0x3Fu << CAN_TXBC_NDTB_Pos) -#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) -#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ -#define CAN_TXBC_TFQS_Msk (0x3Fu << CAN_TXBC_TFQS_Pos) -#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) -#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ -#define CAN_TXBC_TFQM (0x1u << CAN_TXBC_TFQM_Pos) -#define CAN_TXBC_MASK 0x7F3FFFFFu /**< \brief (CAN_TXBC) MASK Register */ - -/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ - uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXFQS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ -#define CAN_TXFQS_RESETVALUE 0x00000000u /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ - -#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ -#define CAN_TXFQS_TFFL_Msk (0x3Fu << CAN_TXFQS_TFFL_Pos) -#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) -#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ -#define CAN_TXFQS_TFGI_Msk (0x1Fu << CAN_TXFQS_TFGI_Pos) -#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) -#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ -#define CAN_TXFQS_TFQPI_Msk (0x1Fu << CAN_TXFQS_TFQPI_Pos) -#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) -#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ -#define CAN_TXFQS_TFQF (0x1u << CAN_TXFQS_TFQF_Pos) -#define CAN_TXFQS_MASK 0x003F1F3Fu /**< \brief (CAN_TXFQS) MASK Register */ - -/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ -#define CAN_TXESC_RESETVALUE 0x00000000u /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ - -#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ -#define CAN_TXESC_TBDS_Msk (0x7u << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) -#define CAN_TXESC_TBDS_DATA8_Val 0x0u /**< \brief (CAN_TXESC) 8 byte data field */ -#define CAN_TXESC_TBDS_DATA12_Val 0x1u /**< \brief (CAN_TXESC) 12 byte data field */ -#define CAN_TXESC_TBDS_DATA16_Val 0x2u /**< \brief (CAN_TXESC) 16 byte data field */ -#define CAN_TXESC_TBDS_DATA20_Val 0x3u /**< \brief (CAN_TXESC) 20 byte data field */ -#define CAN_TXESC_TBDS_DATA24_Val 0x4u /**< \brief (CAN_TXESC) 24 byte data field */ -#define CAN_TXESC_TBDS_DATA32_Val 0x5u /**< \brief (CAN_TXESC) 32 byte data field */ -#define CAN_TXESC_TBDS_DATA48_Val 0x6u /**< \brief (CAN_TXESC) 48 byte data field */ -#define CAN_TXESC_TBDS_DATA64_Val 0x7u /**< \brief (CAN_TXESC) 64 byte data field */ -#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_MASK 0x00000007u /**< \brief (CAN_TXESC) MASK Register */ - -/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ - uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ - uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ - uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ - uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ - uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ - uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ - uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ - uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ - uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ - uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ - uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ - uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ - uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ - uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ - uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ - uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ - uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ - uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ - uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ - uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ - uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ - uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ - uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ - uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ - uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ - uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ - uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ - uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ - uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ - uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ - uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBRP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ -#define CAN_TXBRP_RESETVALUE 0x00000000u /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ - -#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ -#define CAN_TXBRP_TRP0 (0x1u << CAN_TXBRP_TRP0_Pos) -#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ -#define CAN_TXBRP_TRP1 (0x1u << CAN_TXBRP_TRP1_Pos) -#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ -#define CAN_TXBRP_TRP2 (0x1u << CAN_TXBRP_TRP2_Pos) -#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ -#define CAN_TXBRP_TRP3 (0x1u << CAN_TXBRP_TRP3_Pos) -#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ -#define CAN_TXBRP_TRP4 (0x1u << CAN_TXBRP_TRP4_Pos) -#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ -#define CAN_TXBRP_TRP5 (0x1u << CAN_TXBRP_TRP5_Pos) -#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ -#define CAN_TXBRP_TRP6 (0x1u << CAN_TXBRP_TRP6_Pos) -#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ -#define CAN_TXBRP_TRP7 (0x1u << CAN_TXBRP_TRP7_Pos) -#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ -#define CAN_TXBRP_TRP8 (0x1u << CAN_TXBRP_TRP8_Pos) -#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ -#define CAN_TXBRP_TRP9 (0x1u << CAN_TXBRP_TRP9_Pos) -#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ -#define CAN_TXBRP_TRP10 (0x1u << CAN_TXBRP_TRP10_Pos) -#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ -#define CAN_TXBRP_TRP11 (0x1u << CAN_TXBRP_TRP11_Pos) -#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ -#define CAN_TXBRP_TRP12 (0x1u << CAN_TXBRP_TRP12_Pos) -#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ -#define CAN_TXBRP_TRP13 (0x1u << CAN_TXBRP_TRP13_Pos) -#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ -#define CAN_TXBRP_TRP14 (0x1u << CAN_TXBRP_TRP14_Pos) -#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ -#define CAN_TXBRP_TRP15 (0x1u << CAN_TXBRP_TRP15_Pos) -#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ -#define CAN_TXBRP_TRP16 (0x1u << CAN_TXBRP_TRP16_Pos) -#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ -#define CAN_TXBRP_TRP17 (0x1u << CAN_TXBRP_TRP17_Pos) -#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ -#define CAN_TXBRP_TRP18 (0x1u << CAN_TXBRP_TRP18_Pos) -#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ -#define CAN_TXBRP_TRP19 (0x1u << CAN_TXBRP_TRP19_Pos) -#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ -#define CAN_TXBRP_TRP20 (0x1u << CAN_TXBRP_TRP20_Pos) -#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ -#define CAN_TXBRP_TRP21 (0x1u << CAN_TXBRP_TRP21_Pos) -#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ -#define CAN_TXBRP_TRP22 (0x1u << CAN_TXBRP_TRP22_Pos) -#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ -#define CAN_TXBRP_TRP23 (0x1u << CAN_TXBRP_TRP23_Pos) -#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ -#define CAN_TXBRP_TRP24 (0x1u << CAN_TXBRP_TRP24_Pos) -#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ -#define CAN_TXBRP_TRP25 (0x1u << CAN_TXBRP_TRP25_Pos) -#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ -#define CAN_TXBRP_TRP26 (0x1u << CAN_TXBRP_TRP26_Pos) -#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ -#define CAN_TXBRP_TRP27 (0x1u << CAN_TXBRP_TRP27_Pos) -#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ -#define CAN_TXBRP_TRP28 (0x1u << CAN_TXBRP_TRP28_Pos) -#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ -#define CAN_TXBRP_TRP29 (0x1u << CAN_TXBRP_TRP29_Pos) -#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ -#define CAN_TXBRP_TRP30 (0x1u << CAN_TXBRP_TRP30_Pos) -#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ -#define CAN_TXBRP_TRP31 (0x1u << CAN_TXBRP_TRP31_Pos) -#define CAN_TXBRP_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBRP) MASK Register */ - -/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ - uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ - uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ - uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ - uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ - uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ - uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ - uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ - uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ - uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ - uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ - uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ - uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ - uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ - uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ - uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ - uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ - uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ - uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ - uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ - uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ - uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ - uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ - uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ - uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ - uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ - uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ - uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ - uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ - uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ - uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ - uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ -#define CAN_TXBAR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ - -#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ -#define CAN_TXBAR_AR0 (0x1u << CAN_TXBAR_AR0_Pos) -#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ -#define CAN_TXBAR_AR1 (0x1u << CAN_TXBAR_AR1_Pos) -#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ -#define CAN_TXBAR_AR2 (0x1u << CAN_TXBAR_AR2_Pos) -#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ -#define CAN_TXBAR_AR3 (0x1u << CAN_TXBAR_AR3_Pos) -#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ -#define CAN_TXBAR_AR4 (0x1u << CAN_TXBAR_AR4_Pos) -#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ -#define CAN_TXBAR_AR5 (0x1u << CAN_TXBAR_AR5_Pos) -#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ -#define CAN_TXBAR_AR6 (0x1u << CAN_TXBAR_AR6_Pos) -#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ -#define CAN_TXBAR_AR7 (0x1u << CAN_TXBAR_AR7_Pos) -#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ -#define CAN_TXBAR_AR8 (0x1u << CAN_TXBAR_AR8_Pos) -#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ -#define CAN_TXBAR_AR9 (0x1u << CAN_TXBAR_AR9_Pos) -#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ -#define CAN_TXBAR_AR10 (0x1u << CAN_TXBAR_AR10_Pos) -#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ -#define CAN_TXBAR_AR11 (0x1u << CAN_TXBAR_AR11_Pos) -#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ -#define CAN_TXBAR_AR12 (0x1u << CAN_TXBAR_AR12_Pos) -#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ -#define CAN_TXBAR_AR13 (0x1u << CAN_TXBAR_AR13_Pos) -#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ -#define CAN_TXBAR_AR14 (0x1u << CAN_TXBAR_AR14_Pos) -#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ -#define CAN_TXBAR_AR15 (0x1u << CAN_TXBAR_AR15_Pos) -#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ -#define CAN_TXBAR_AR16 (0x1u << CAN_TXBAR_AR16_Pos) -#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ -#define CAN_TXBAR_AR17 (0x1u << CAN_TXBAR_AR17_Pos) -#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ -#define CAN_TXBAR_AR18 (0x1u << CAN_TXBAR_AR18_Pos) -#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ -#define CAN_TXBAR_AR19 (0x1u << CAN_TXBAR_AR19_Pos) -#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ -#define CAN_TXBAR_AR20 (0x1u << CAN_TXBAR_AR20_Pos) -#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ -#define CAN_TXBAR_AR21 (0x1u << CAN_TXBAR_AR21_Pos) -#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ -#define CAN_TXBAR_AR22 (0x1u << CAN_TXBAR_AR22_Pos) -#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ -#define CAN_TXBAR_AR23 (0x1u << CAN_TXBAR_AR23_Pos) -#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ -#define CAN_TXBAR_AR24 (0x1u << CAN_TXBAR_AR24_Pos) -#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ -#define CAN_TXBAR_AR25 (0x1u << CAN_TXBAR_AR25_Pos) -#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ -#define CAN_TXBAR_AR26 (0x1u << CAN_TXBAR_AR26_Pos) -#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ -#define CAN_TXBAR_AR27 (0x1u << CAN_TXBAR_AR27_Pos) -#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ -#define CAN_TXBAR_AR28 (0x1u << CAN_TXBAR_AR28_Pos) -#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ -#define CAN_TXBAR_AR29 (0x1u << CAN_TXBAR_AR29_Pos) -#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ -#define CAN_TXBAR_AR30 (0x1u << CAN_TXBAR_AR30_Pos) -#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ -#define CAN_TXBAR_AR31 (0x1u << CAN_TXBAR_AR31_Pos) -#define CAN_TXBAR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBAR) MASK Register */ - -/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ - uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ - uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ - uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ - uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ - uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ - uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ - uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ - uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ - uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ - uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ - uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ - uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ - uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ - uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ - uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ - uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ - uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ - uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ - uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ - uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ - uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ - uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ - uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ - uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ - uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ - uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ - uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ - uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ - uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ - uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ - uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ -#define CAN_TXBCR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ - -#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ -#define CAN_TXBCR_CR0 (0x1u << CAN_TXBCR_CR0_Pos) -#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ -#define CAN_TXBCR_CR1 (0x1u << CAN_TXBCR_CR1_Pos) -#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ -#define CAN_TXBCR_CR2 (0x1u << CAN_TXBCR_CR2_Pos) -#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ -#define CAN_TXBCR_CR3 (0x1u << CAN_TXBCR_CR3_Pos) -#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ -#define CAN_TXBCR_CR4 (0x1u << CAN_TXBCR_CR4_Pos) -#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ -#define CAN_TXBCR_CR5 (0x1u << CAN_TXBCR_CR5_Pos) -#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ -#define CAN_TXBCR_CR6 (0x1u << CAN_TXBCR_CR6_Pos) -#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ -#define CAN_TXBCR_CR7 (0x1u << CAN_TXBCR_CR7_Pos) -#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ -#define CAN_TXBCR_CR8 (0x1u << CAN_TXBCR_CR8_Pos) -#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ -#define CAN_TXBCR_CR9 (0x1u << CAN_TXBCR_CR9_Pos) -#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ -#define CAN_TXBCR_CR10 (0x1u << CAN_TXBCR_CR10_Pos) -#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ -#define CAN_TXBCR_CR11 (0x1u << CAN_TXBCR_CR11_Pos) -#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ -#define CAN_TXBCR_CR12 (0x1u << CAN_TXBCR_CR12_Pos) -#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ -#define CAN_TXBCR_CR13 (0x1u << CAN_TXBCR_CR13_Pos) -#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ -#define CAN_TXBCR_CR14 (0x1u << CAN_TXBCR_CR14_Pos) -#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ -#define CAN_TXBCR_CR15 (0x1u << CAN_TXBCR_CR15_Pos) -#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ -#define CAN_TXBCR_CR16 (0x1u << CAN_TXBCR_CR16_Pos) -#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ -#define CAN_TXBCR_CR17 (0x1u << CAN_TXBCR_CR17_Pos) -#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ -#define CAN_TXBCR_CR18 (0x1u << CAN_TXBCR_CR18_Pos) -#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ -#define CAN_TXBCR_CR19 (0x1u << CAN_TXBCR_CR19_Pos) -#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ -#define CAN_TXBCR_CR20 (0x1u << CAN_TXBCR_CR20_Pos) -#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ -#define CAN_TXBCR_CR21 (0x1u << CAN_TXBCR_CR21_Pos) -#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ -#define CAN_TXBCR_CR22 (0x1u << CAN_TXBCR_CR22_Pos) -#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ -#define CAN_TXBCR_CR23 (0x1u << CAN_TXBCR_CR23_Pos) -#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ -#define CAN_TXBCR_CR24 (0x1u << CAN_TXBCR_CR24_Pos) -#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ -#define CAN_TXBCR_CR25 (0x1u << CAN_TXBCR_CR25_Pos) -#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ -#define CAN_TXBCR_CR26 (0x1u << CAN_TXBCR_CR26_Pos) -#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ -#define CAN_TXBCR_CR27 (0x1u << CAN_TXBCR_CR27_Pos) -#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ -#define CAN_TXBCR_CR28 (0x1u << CAN_TXBCR_CR28_Pos) -#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ -#define CAN_TXBCR_CR29 (0x1u << CAN_TXBCR_CR29_Pos) -#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ -#define CAN_TXBCR_CR30 (0x1u << CAN_TXBCR_CR30_Pos) -#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ -#define CAN_TXBCR_CR31 (0x1u << CAN_TXBCR_CR31_Pos) -#define CAN_TXBCR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCR) MASK Register */ - -/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ - uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ - uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ - uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ - uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ - uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ - uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ - uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ - uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ - uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ - uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ - uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ - uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ - uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ - uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ - uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ - uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ - uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ - uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ - uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ - uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ - uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ - uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ - uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ - uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ - uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ - uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ - uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ - uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ - uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ - uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ - uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ -#define CAN_TXBTO_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ - -#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ -#define CAN_TXBTO_TO0 (0x1u << CAN_TXBTO_TO0_Pos) -#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ -#define CAN_TXBTO_TO1 (0x1u << CAN_TXBTO_TO1_Pos) -#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ -#define CAN_TXBTO_TO2 (0x1u << CAN_TXBTO_TO2_Pos) -#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ -#define CAN_TXBTO_TO3 (0x1u << CAN_TXBTO_TO3_Pos) -#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ -#define CAN_TXBTO_TO4 (0x1u << CAN_TXBTO_TO4_Pos) -#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ -#define CAN_TXBTO_TO5 (0x1u << CAN_TXBTO_TO5_Pos) -#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ -#define CAN_TXBTO_TO6 (0x1u << CAN_TXBTO_TO6_Pos) -#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ -#define CAN_TXBTO_TO7 (0x1u << CAN_TXBTO_TO7_Pos) -#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ -#define CAN_TXBTO_TO8 (0x1u << CAN_TXBTO_TO8_Pos) -#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ -#define CAN_TXBTO_TO9 (0x1u << CAN_TXBTO_TO9_Pos) -#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ -#define CAN_TXBTO_TO10 (0x1u << CAN_TXBTO_TO10_Pos) -#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ -#define CAN_TXBTO_TO11 (0x1u << CAN_TXBTO_TO11_Pos) -#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ -#define CAN_TXBTO_TO12 (0x1u << CAN_TXBTO_TO12_Pos) -#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ -#define CAN_TXBTO_TO13 (0x1u << CAN_TXBTO_TO13_Pos) -#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ -#define CAN_TXBTO_TO14 (0x1u << CAN_TXBTO_TO14_Pos) -#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ -#define CAN_TXBTO_TO15 (0x1u << CAN_TXBTO_TO15_Pos) -#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ -#define CAN_TXBTO_TO16 (0x1u << CAN_TXBTO_TO16_Pos) -#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ -#define CAN_TXBTO_TO17 (0x1u << CAN_TXBTO_TO17_Pos) -#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ -#define CAN_TXBTO_TO18 (0x1u << CAN_TXBTO_TO18_Pos) -#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ -#define CAN_TXBTO_TO19 (0x1u << CAN_TXBTO_TO19_Pos) -#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ -#define CAN_TXBTO_TO20 (0x1u << CAN_TXBTO_TO20_Pos) -#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ -#define CAN_TXBTO_TO21 (0x1u << CAN_TXBTO_TO21_Pos) -#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ -#define CAN_TXBTO_TO22 (0x1u << CAN_TXBTO_TO22_Pos) -#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ -#define CAN_TXBTO_TO23 (0x1u << CAN_TXBTO_TO23_Pos) -#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ -#define CAN_TXBTO_TO24 (0x1u << CAN_TXBTO_TO24_Pos) -#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ -#define CAN_TXBTO_TO25 (0x1u << CAN_TXBTO_TO25_Pos) -#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ -#define CAN_TXBTO_TO26 (0x1u << CAN_TXBTO_TO26_Pos) -#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ -#define CAN_TXBTO_TO27 (0x1u << CAN_TXBTO_TO27_Pos) -#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ -#define CAN_TXBTO_TO28 (0x1u << CAN_TXBTO_TO28_Pos) -#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ -#define CAN_TXBTO_TO29 (0x1u << CAN_TXBTO_TO29_Pos) -#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ -#define CAN_TXBTO_TO30 (0x1u << CAN_TXBTO_TO30_Pos) -#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ -#define CAN_TXBTO_TO31 (0x1u << CAN_TXBTO_TO31_Pos) -#define CAN_TXBTO_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTO) MASK Register */ - -/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ - uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ - uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ - uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ - uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ - uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ - uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ - uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ - uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ - uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ - uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ - uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ - uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ - uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ - uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ - uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ - uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ - uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ - uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ - uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ - uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ - uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ - uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ - uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ - uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ - uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ - uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ - uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ - uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ - uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ - uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ - uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ -#define CAN_TXBCF_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ - -#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ -#define CAN_TXBCF_CF0 (0x1u << CAN_TXBCF_CF0_Pos) -#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ -#define CAN_TXBCF_CF1 (0x1u << CAN_TXBCF_CF1_Pos) -#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ -#define CAN_TXBCF_CF2 (0x1u << CAN_TXBCF_CF2_Pos) -#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ -#define CAN_TXBCF_CF3 (0x1u << CAN_TXBCF_CF3_Pos) -#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ -#define CAN_TXBCF_CF4 (0x1u << CAN_TXBCF_CF4_Pos) -#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ -#define CAN_TXBCF_CF5 (0x1u << CAN_TXBCF_CF5_Pos) -#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ -#define CAN_TXBCF_CF6 (0x1u << CAN_TXBCF_CF6_Pos) -#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ -#define CAN_TXBCF_CF7 (0x1u << CAN_TXBCF_CF7_Pos) -#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ -#define CAN_TXBCF_CF8 (0x1u << CAN_TXBCF_CF8_Pos) -#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ -#define CAN_TXBCF_CF9 (0x1u << CAN_TXBCF_CF9_Pos) -#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ -#define CAN_TXBCF_CF10 (0x1u << CAN_TXBCF_CF10_Pos) -#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ -#define CAN_TXBCF_CF11 (0x1u << CAN_TXBCF_CF11_Pos) -#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ -#define CAN_TXBCF_CF12 (0x1u << CAN_TXBCF_CF12_Pos) -#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ -#define CAN_TXBCF_CF13 (0x1u << CAN_TXBCF_CF13_Pos) -#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ -#define CAN_TXBCF_CF14 (0x1u << CAN_TXBCF_CF14_Pos) -#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ -#define CAN_TXBCF_CF15 (0x1u << CAN_TXBCF_CF15_Pos) -#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ -#define CAN_TXBCF_CF16 (0x1u << CAN_TXBCF_CF16_Pos) -#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ -#define CAN_TXBCF_CF17 (0x1u << CAN_TXBCF_CF17_Pos) -#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ -#define CAN_TXBCF_CF18 (0x1u << CAN_TXBCF_CF18_Pos) -#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ -#define CAN_TXBCF_CF19 (0x1u << CAN_TXBCF_CF19_Pos) -#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ -#define CAN_TXBCF_CF20 (0x1u << CAN_TXBCF_CF20_Pos) -#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ -#define CAN_TXBCF_CF21 (0x1u << CAN_TXBCF_CF21_Pos) -#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ -#define CAN_TXBCF_CF22 (0x1u << CAN_TXBCF_CF22_Pos) -#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ -#define CAN_TXBCF_CF23 (0x1u << CAN_TXBCF_CF23_Pos) -#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ -#define CAN_TXBCF_CF24 (0x1u << CAN_TXBCF_CF24_Pos) -#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ -#define CAN_TXBCF_CF25 (0x1u << CAN_TXBCF_CF25_Pos) -#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ -#define CAN_TXBCF_CF26 (0x1u << CAN_TXBCF_CF26_Pos) -#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ -#define CAN_TXBCF_CF27 (0x1u << CAN_TXBCF_CF27_Pos) -#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ -#define CAN_TXBCF_CF28 (0x1u << CAN_TXBCF_CF28_Pos) -#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ -#define CAN_TXBCF_CF29 (0x1u << CAN_TXBCF_CF29_Pos) -#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ -#define CAN_TXBCF_CF30 (0x1u << CAN_TXBCF_CF30_Pos) -#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ -#define CAN_TXBCF_CF31 (0x1u << CAN_TXBCF_CF31_Pos) -#define CAN_TXBCF_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCF) MASK Register */ - -/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ - uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ - uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ - uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ - uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ - uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ - uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ - uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ - uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ - uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ - uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ - uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ - uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ - uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ - uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ - uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ - uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ - uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ - uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ - uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ - uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ - uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ - uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ - uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ - uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ - uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ - uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ - uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ - uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ - uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ - uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ - uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ -#define CAN_TXBTIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ - -#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ -#define CAN_TXBTIE_TIE0 (0x1u << CAN_TXBTIE_TIE0_Pos) -#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ -#define CAN_TXBTIE_TIE1 (0x1u << CAN_TXBTIE_TIE1_Pos) -#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ -#define CAN_TXBTIE_TIE2 (0x1u << CAN_TXBTIE_TIE2_Pos) -#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ -#define CAN_TXBTIE_TIE3 (0x1u << CAN_TXBTIE_TIE3_Pos) -#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ -#define CAN_TXBTIE_TIE4 (0x1u << CAN_TXBTIE_TIE4_Pos) -#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ -#define CAN_TXBTIE_TIE5 (0x1u << CAN_TXBTIE_TIE5_Pos) -#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ -#define CAN_TXBTIE_TIE6 (0x1u << CAN_TXBTIE_TIE6_Pos) -#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ -#define CAN_TXBTIE_TIE7 (0x1u << CAN_TXBTIE_TIE7_Pos) -#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ -#define CAN_TXBTIE_TIE8 (0x1u << CAN_TXBTIE_TIE8_Pos) -#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ -#define CAN_TXBTIE_TIE9 (0x1u << CAN_TXBTIE_TIE9_Pos) -#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ -#define CAN_TXBTIE_TIE10 (0x1u << CAN_TXBTIE_TIE10_Pos) -#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ -#define CAN_TXBTIE_TIE11 (0x1u << CAN_TXBTIE_TIE11_Pos) -#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ -#define CAN_TXBTIE_TIE12 (0x1u << CAN_TXBTIE_TIE12_Pos) -#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ -#define CAN_TXBTIE_TIE13 (0x1u << CAN_TXBTIE_TIE13_Pos) -#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ -#define CAN_TXBTIE_TIE14 (0x1u << CAN_TXBTIE_TIE14_Pos) -#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ -#define CAN_TXBTIE_TIE15 (0x1u << CAN_TXBTIE_TIE15_Pos) -#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ -#define CAN_TXBTIE_TIE16 (0x1u << CAN_TXBTIE_TIE16_Pos) -#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ -#define CAN_TXBTIE_TIE17 (0x1u << CAN_TXBTIE_TIE17_Pos) -#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ -#define CAN_TXBTIE_TIE18 (0x1u << CAN_TXBTIE_TIE18_Pos) -#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ -#define CAN_TXBTIE_TIE19 (0x1u << CAN_TXBTIE_TIE19_Pos) -#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ -#define CAN_TXBTIE_TIE20 (0x1u << CAN_TXBTIE_TIE20_Pos) -#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ -#define CAN_TXBTIE_TIE21 (0x1u << CAN_TXBTIE_TIE21_Pos) -#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ -#define CAN_TXBTIE_TIE22 (0x1u << CAN_TXBTIE_TIE22_Pos) -#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ -#define CAN_TXBTIE_TIE23 (0x1u << CAN_TXBTIE_TIE23_Pos) -#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ -#define CAN_TXBTIE_TIE24 (0x1u << CAN_TXBTIE_TIE24_Pos) -#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ -#define CAN_TXBTIE_TIE25 (0x1u << CAN_TXBTIE_TIE25_Pos) -#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ -#define CAN_TXBTIE_TIE26 (0x1u << CAN_TXBTIE_TIE26_Pos) -#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ -#define CAN_TXBTIE_TIE27 (0x1u << CAN_TXBTIE_TIE27_Pos) -#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ -#define CAN_TXBTIE_TIE28 (0x1u << CAN_TXBTIE_TIE28_Pos) -#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ -#define CAN_TXBTIE_TIE29 (0x1u << CAN_TXBTIE_TIE29_Pos) -#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ -#define CAN_TXBTIE_TIE30 (0x1u << CAN_TXBTIE_TIE30_Pos) -#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ -#define CAN_TXBTIE_TIE31 (0x1u << CAN_TXBTIE_TIE31_Pos) -#define CAN_TXBTIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTIE) MASK Register */ - -/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ - uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ - uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ - uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ - uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ - uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ - uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ - uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ - uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ - uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ - uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ - uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ - uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ - uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ - uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ - uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ - uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ - uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ - uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ - uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ - uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ - uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ - uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ - uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ - uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ - uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ - uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ - uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ - uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ - uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ - uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ - uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ -#define CAN_TXBCIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ - -#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ -#define CAN_TXBCIE_CFIE0 (0x1u << CAN_TXBCIE_CFIE0_Pos) -#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ -#define CAN_TXBCIE_CFIE1 (0x1u << CAN_TXBCIE_CFIE1_Pos) -#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ -#define CAN_TXBCIE_CFIE2 (0x1u << CAN_TXBCIE_CFIE2_Pos) -#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ -#define CAN_TXBCIE_CFIE3 (0x1u << CAN_TXBCIE_CFIE3_Pos) -#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ -#define CAN_TXBCIE_CFIE4 (0x1u << CAN_TXBCIE_CFIE4_Pos) -#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ -#define CAN_TXBCIE_CFIE5 (0x1u << CAN_TXBCIE_CFIE5_Pos) -#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ -#define CAN_TXBCIE_CFIE6 (0x1u << CAN_TXBCIE_CFIE6_Pos) -#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ -#define CAN_TXBCIE_CFIE7 (0x1u << CAN_TXBCIE_CFIE7_Pos) -#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ -#define CAN_TXBCIE_CFIE8 (0x1u << CAN_TXBCIE_CFIE8_Pos) -#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ -#define CAN_TXBCIE_CFIE9 (0x1u << CAN_TXBCIE_CFIE9_Pos) -#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ -#define CAN_TXBCIE_CFIE10 (0x1u << CAN_TXBCIE_CFIE10_Pos) -#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ -#define CAN_TXBCIE_CFIE11 (0x1u << CAN_TXBCIE_CFIE11_Pos) -#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ -#define CAN_TXBCIE_CFIE12 (0x1u << CAN_TXBCIE_CFIE12_Pos) -#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ -#define CAN_TXBCIE_CFIE13 (0x1u << CAN_TXBCIE_CFIE13_Pos) -#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ -#define CAN_TXBCIE_CFIE14 (0x1u << CAN_TXBCIE_CFIE14_Pos) -#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ -#define CAN_TXBCIE_CFIE15 (0x1u << CAN_TXBCIE_CFIE15_Pos) -#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ -#define CAN_TXBCIE_CFIE16 (0x1u << CAN_TXBCIE_CFIE16_Pos) -#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ -#define CAN_TXBCIE_CFIE17 (0x1u << CAN_TXBCIE_CFIE17_Pos) -#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ -#define CAN_TXBCIE_CFIE18 (0x1u << CAN_TXBCIE_CFIE18_Pos) -#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ -#define CAN_TXBCIE_CFIE19 (0x1u << CAN_TXBCIE_CFIE19_Pos) -#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ -#define CAN_TXBCIE_CFIE20 (0x1u << CAN_TXBCIE_CFIE20_Pos) -#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ -#define CAN_TXBCIE_CFIE21 (0x1u << CAN_TXBCIE_CFIE21_Pos) -#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ -#define CAN_TXBCIE_CFIE22 (0x1u << CAN_TXBCIE_CFIE22_Pos) -#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ -#define CAN_TXBCIE_CFIE23 (0x1u << CAN_TXBCIE_CFIE23_Pos) -#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ -#define CAN_TXBCIE_CFIE24 (0x1u << CAN_TXBCIE_CFIE24_Pos) -#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ -#define CAN_TXBCIE_CFIE25 (0x1u << CAN_TXBCIE_CFIE25_Pos) -#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ -#define CAN_TXBCIE_CFIE26 (0x1u << CAN_TXBCIE_CFIE26_Pos) -#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ -#define CAN_TXBCIE_CFIE27 (0x1u << CAN_TXBCIE_CFIE27_Pos) -#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ -#define CAN_TXBCIE_CFIE28 (0x1u << CAN_TXBCIE_CFIE28_Pos) -#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ -#define CAN_TXBCIE_CFIE29 (0x1u << CAN_TXBCIE_CFIE29_Pos) -#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ -#define CAN_TXBCIE_CFIE30 (0x1u << CAN_TXBCIE_CFIE30_Pos) -#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ -#define CAN_TXBCIE_CFIE31 (0x1u << CAN_TXBCIE_CFIE31_Pos) -#define CAN_TXBCIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCIE) MASK Register */ - -/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ - uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ -#define CAN_TXEFC_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ - -#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ -#define CAN_TXEFC_EFSA_Msk (0xFFFFu << CAN_TXEFC_EFSA_Pos) -#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) -#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ -#define CAN_TXEFC_EFS_Msk (0x3Fu << CAN_TXEFC_EFS_Pos) -#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) -#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ -#define CAN_TXEFC_EFWM_Msk (0x3Fu << CAN_TXEFC_EFWM_Pos) -#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) -#define CAN_TXEFC_MASK 0x3F3FFFFFu /**< \brief (CAN_TXEFC) MASK Register */ - -/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ - uint32_t :3; /*!< bit: 21..23 Reserved */ - uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ -#define CAN_TXEFS_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ - -#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ -#define CAN_TXEFS_EFFL_Msk (0x3Fu << CAN_TXEFS_EFFL_Pos) -#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) -#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ -#define CAN_TXEFS_EFGI_Msk (0x1Fu << CAN_TXEFS_EFGI_Pos) -#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) -#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ -#define CAN_TXEFS_EFPI_Msk (0x1Fu << CAN_TXEFS_EFPI_Pos) -#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) -#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ -#define CAN_TXEFS_EFF (0x1u << CAN_TXEFS_EFF_Pos) -#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ -#define CAN_TXEFS_TEFL (0x1u << CAN_TXEFS_TEFL_Pos) -#define CAN_TXEFS_MASK 0x031F1F3Fu /**< \brief (CAN_TXEFS) MASK Register */ - -/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ -#define CAN_TXEFA_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ - -#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ -#define CAN_TXEFA_EFAI_Msk (0x1Fu << CAN_TXEFA_EFAI_Pos) -#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) -#define CAN_TXEFA_MASK 0x0000001Fu /**< \brief (CAN_TXEFA) MASK Register */ - -/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ -#define CAN_RXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ - -#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ -#define CAN_RXBE_0_ID_Msk (0x1FFFFFFFu << CAN_RXBE_0_ID_Pos) -#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) -#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ -#define CAN_RXBE_0_RTR (0x1u << CAN_RXBE_0_RTR_Pos) -#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ -#define CAN_RXBE_0_XTD (0x1u << CAN_RXBE_0_XTD_Pos) -#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ -#define CAN_RXBE_0_ESI (0x1u << CAN_RXBE_0_ESI_Pos) -#define CAN_RXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_0) MASK Register */ - -/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ -#define CAN_RXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ - -#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ -#define CAN_RXBE_1_RXTS_Msk (0xFFFFu << CAN_RXBE_1_RXTS_Pos) -#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) -#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ -#define CAN_RXBE_1_DLC_Msk (0xFu << CAN_RXBE_1_DLC_Pos) -#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) -#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ -#define CAN_RXBE_1_BRS (0x1u << CAN_RXBE_1_BRS_Pos) -#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ -#define CAN_RXBE_1_FDF (0x1u << CAN_RXBE_1_FDF_Pos) -#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ -#define CAN_RXBE_1_FIDX_Msk (0x7Fu << CAN_RXBE_1_FIDX_Pos) -#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) -#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ -#define CAN_RXBE_1_ANMF (0x1u << CAN_RXBE_1_ANMF_Pos) -#define CAN_RXBE_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXBE_1) MASK Register */ - -/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ -#define CAN_RXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ - -#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ -#define CAN_RXBE_DATA_DB0_Msk (0xFFu << CAN_RXBE_DATA_DB0_Pos) -#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) -#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ -#define CAN_RXBE_DATA_DB1_Msk (0xFFu << CAN_RXBE_DATA_DB1_Pos) -#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) -#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ -#define CAN_RXBE_DATA_DB2_Msk (0xFFu << CAN_RXBE_DATA_DB2_Pos) -#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) -#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ -#define CAN_RXBE_DATA_DB3_Msk (0xFFu << CAN_RXBE_DATA_DB3_Pos) -#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) -#define CAN_RXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_DATA) MASK Register */ - -/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ -#define CAN_RXF0E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ - -#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ -#define CAN_RXF0E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF0E_0_ID_Pos) -#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) -#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ -#define CAN_RXF0E_0_RTR (0x1u << CAN_RXF0E_0_RTR_Pos) -#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ -#define CAN_RXF0E_0_XTD (0x1u << CAN_RXF0E_0_XTD_Pos) -#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ -#define CAN_RXF0E_0_ESI (0x1u << CAN_RXF0E_0_ESI_Pos) -#define CAN_RXF0E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_0) MASK Register */ - -/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ -#define CAN_RXF0E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ - -#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ -#define CAN_RXF0E_1_RXTS_Msk (0xFFFFu << CAN_RXF0E_1_RXTS_Pos) -#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) -#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ -#define CAN_RXF0E_1_DLC_Msk (0xFu << CAN_RXF0E_1_DLC_Pos) -#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) -#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ -#define CAN_RXF0E_1_BRS (0x1u << CAN_RXF0E_1_BRS_Pos) -#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ -#define CAN_RXF0E_1_FDF (0x1u << CAN_RXF0E_1_FDF_Pos) -#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ -#define CAN_RXF0E_1_FIDX_Msk (0x7Fu << CAN_RXF0E_1_FIDX_Pos) -#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) -#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ -#define CAN_RXF0E_1_ANMF (0x1u << CAN_RXF0E_1_ANMF_Pos) -#define CAN_RXF0E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF0E_1) MASK Register */ - -/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ -#define CAN_RXF0E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ - -#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ -#define CAN_RXF0E_DATA_DB0_Msk (0xFFu << CAN_RXF0E_DATA_DB0_Pos) -#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) -#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ -#define CAN_RXF0E_DATA_DB1_Msk (0xFFu << CAN_RXF0E_DATA_DB1_Pos) -#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) -#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ -#define CAN_RXF0E_DATA_DB2_Msk (0xFFu << CAN_RXF0E_DATA_DB2_Pos) -#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) -#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ -#define CAN_RXF0E_DATA_DB3_Msk (0xFFu << CAN_RXF0E_DATA_DB3_Pos) -#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) -#define CAN_RXF0E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_DATA) MASK Register */ - -/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ -#define CAN_RXF1E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ - -#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ -#define CAN_RXF1E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF1E_0_ID_Pos) -#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) -#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ -#define CAN_RXF1E_0_RTR (0x1u << CAN_RXF1E_0_RTR_Pos) -#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ -#define CAN_RXF1E_0_XTD (0x1u << CAN_RXF1E_0_XTD_Pos) -#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ -#define CAN_RXF1E_0_ESI (0x1u << CAN_RXF1E_0_ESI_Pos) -#define CAN_RXF1E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_0) MASK Register */ - -/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ -#define CAN_RXF1E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ - -#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ -#define CAN_RXF1E_1_RXTS_Msk (0xFFFFu << CAN_RXF1E_1_RXTS_Pos) -#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) -#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ -#define CAN_RXF1E_1_DLC_Msk (0xFu << CAN_RXF1E_1_DLC_Pos) -#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) -#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ -#define CAN_RXF1E_1_BRS (0x1u << CAN_RXF1E_1_BRS_Pos) -#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ -#define CAN_RXF1E_1_FDF (0x1u << CAN_RXF1E_1_FDF_Pos) -#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ -#define CAN_RXF1E_1_FIDX_Msk (0x7Fu << CAN_RXF1E_1_FIDX_Pos) -#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) -#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ -#define CAN_RXF1E_1_ANMF (0x1u << CAN_RXF1E_1_ANMF_Pos) -#define CAN_RXF1E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF1E_1) MASK Register */ - -/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ -#define CAN_RXF1E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ - -#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ -#define CAN_RXF1E_DATA_DB0_Msk (0xFFu << CAN_RXF1E_DATA_DB0_Pos) -#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) -#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ -#define CAN_RXF1E_DATA_DB1_Msk (0xFFu << CAN_RXF1E_DATA_DB1_Pos) -#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) -#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ -#define CAN_RXF1E_DATA_DB2_Msk (0xFFu << CAN_RXF1E_DATA_DB2_Pos) -#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) -#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ -#define CAN_RXF1E_DATA_DB3_Msk (0xFFu << CAN_RXF1E_DATA_DB3_Pos) -#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) -#define CAN_RXF1E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_DATA) MASK Register */ - -/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ - uint32_t :5; /*!< bit: 11..15 Reserved */ - uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ - uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ - uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ -#define CAN_SIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ - -#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ -#define CAN_SIDFE_0_SFID2_Msk (0x7FFu << CAN_SIDFE_0_SFID2_Pos) -#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) -#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ -#define CAN_SIDFE_0_SFID1_Msk (0x7FFu << CAN_SIDFE_0_SFID1_Pos) -#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) -#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ -#define CAN_SIDFE_0_SFEC_Msk (0x7u << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) -#define CAN_SIDFE_0_SFEC_DISABLE_Val 0x0u /**< \brief (CAN_SIDFE_0) Disable filter element */ -#define CAN_SIDFE_0_SFEC_STF0M_Val 0x1u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_STF1M_Val 0x2u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_REJECT_Val 0x3u /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ -#define CAN_SIDFE_0_SFEC_PRIORITY_Val 0x4u /**< \brief (CAN_SIDFE_0) Set priority if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF0M_Val 0x5u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF1M_Val 0x6u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_STRXBUF_Val 0x7u /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ -#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ -#define CAN_SIDFE_0_SFT_Msk (0x3u << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) -#define CAN_SIDFE_0_SFT_RANGE_Val 0x0u /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ -#define CAN_SIDFE_0_SFT_DUAL_Val 0x1u /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ -#define CAN_SIDFE_0_SFT_CLASSIC_Val 0x2u /**< \brief (CAN_SIDFE_0) Classic filter */ -#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_MASK 0xFFFF07FFu /**< \brief (CAN_SIDFE_0) MASK Register */ - -/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ -#define CAN_TXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ - -#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ -#define CAN_TXBE_0_ID_Msk (0x1FFFFFFFu << CAN_TXBE_0_ID_Pos) -#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) -#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ -#define CAN_TXBE_0_RTR (0x1u << CAN_TXBE_0_RTR_Pos) -#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ -#define CAN_TXBE_0_XTD (0x1u << CAN_TXBE_0_XTD_Pos) -#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ -#define CAN_TXBE_0_ESI (0x1u << CAN_TXBE_0_ESI_Pos) -#define CAN_TXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_0) MASK Register */ - -/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t DLC:4; /*!< bit: 16..19 Identifier */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ -#define CAN_TXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ - -#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ -#define CAN_TXBE_1_DLC_Msk (0xFu << CAN_TXBE_1_DLC_Pos) -#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) -#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ -#define CAN_TXBE_1_BRS (0x1u << CAN_TXBE_1_BRS_Pos) -#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ -#define CAN_TXBE_1_FDF (0x1u << CAN_TXBE_1_FDF_Pos) -#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ -#define CAN_TXBE_1_EFC (0x1u << CAN_TXBE_1_EFC_Pos) -#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ -#define CAN_TXBE_1_MM_Msk (0xFFu << CAN_TXBE_1_MM_Pos) -#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) -#define CAN_TXBE_1_MASK 0xFFBF0000u /**< \brief (CAN_TXBE_1) MASK Register */ - -/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ -#define CAN_TXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ - -#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ -#define CAN_TXBE_DATA_DB0_Msk (0xFFu << CAN_TXBE_DATA_DB0_Pos) -#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) -#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ -#define CAN_TXBE_DATA_DB1_Msk (0xFFu << CAN_TXBE_DATA_DB1_Pos) -#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) -#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ -#define CAN_TXBE_DATA_DB2_Msk (0xFFu << CAN_TXBE_DATA_DB2_Pos) -#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) -#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ -#define CAN_TXBE_DATA_DB3_Msk (0xFFu << CAN_TXBE_DATA_DB3_Pos) -#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) -#define CAN_TXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_DATA) MASK Register */ - -/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ -#define CAN_TXEFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ - -#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ -#define CAN_TXEFE_0_ID_Msk (0x1FFFFFFFu << CAN_TXEFE_0_ID_Pos) -#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) -#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ -#define CAN_TXEFE_0_RTR (0x1u << CAN_TXEFE_0_RTR_Pos) -#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ -#define CAN_TXEFE_0_XTD (0x1u << CAN_TXEFE_0_XTD_Pos) -#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ -#define CAN_TXEFE_0_ESI (0x1u << CAN_TXEFE_0_ESI_Pos) -#define CAN_TXEFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_0) MASK Register */ - -/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t ET:2; /*!< bit: 22..23 Event Type */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ -#define CAN_TXEFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ - -#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ -#define CAN_TXEFE_1_TXTS_Msk (0xFFFFu << CAN_TXEFE_1_TXTS_Pos) -#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) -#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ -#define CAN_TXEFE_1_DLC_Msk (0xFu << CAN_TXEFE_1_DLC_Pos) -#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) -#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ -#define CAN_TXEFE_1_BRS (0x1u << CAN_TXEFE_1_BRS_Pos) -#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ -#define CAN_TXEFE_1_FDF (0x1u << CAN_TXEFE_1_FDF_Pos) -#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ -#define CAN_TXEFE_1_ET_Msk (0x3u << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) -#define CAN_TXEFE_1_ET_TXE_Val 0x1u /**< \brief (CAN_TXEFE_1) Tx event */ -#define CAN_TXEFE_1_ET_TXC_Val 0x2u /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ -#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ -#define CAN_TXEFE_1_MM_Msk (0xFFu << CAN_TXEFE_1_MM_Pos) -#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) -#define CAN_TXEFE_1_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_1) MASK Register */ - -/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ - uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ -#define CAN_XIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ - -#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ -#define CAN_XIDFE_0_EFID1_Msk (0x1FFFFFFFu << CAN_XIDFE_0_EFID1_Pos) -#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) -#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ -#define CAN_XIDFE_0_EFEC_Msk (0x7u << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) -#define CAN_XIDFE_0_EFEC_DISABLE_Val 0x0u /**< \brief (CAN_XIDFE_0) Disable filter element */ -#define CAN_XIDFE_0_EFEC_STF0M_Val 0x1u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_STF1M_Val 0x2u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_REJECT_Val 0x3u /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ -#define CAN_XIDFE_0_EFEC_PRIORITY_Val 0x4u /**< \brief (CAN_XIDFE_0) Set priority if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF0M_Val 0x5u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF1M_Val 0x6u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_STRXBUF_Val 0x7u /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ -#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_XIDFE_0) MASK Register */ - -/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ -#define CAN_XIDFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ - -#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ -#define CAN_XIDFE_1_EFID2_Msk (0x1FFFFFFFu << CAN_XIDFE_1_EFID2_Pos) -#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) -#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ -#define CAN_XIDFE_1_EFT_Msk (0x3u << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) -#define CAN_XIDFE_1_EFT_RANGEM_Val 0x0u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ -#define CAN_XIDFE_1_EFT_DUAL_Val 0x1u /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ -#define CAN_XIDFE_1_EFT_CLASSIC_Val 0x2u /**< \brief (CAN_XIDFE_1) Classic filter */ -#define CAN_XIDFE_1_EFT_RANGE_Val 0x3u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ -#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_MASK 0xDFFFFFFFu /**< \brief (CAN_XIDFE_1) MASK Register */ - -/** \brief CAN APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ - __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ - __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ - __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ - __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ - __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ - __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ - __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ - __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ - __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ - __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ - __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ - RoReg8 Reserved1[0x10]; - __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ - __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ - __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved2[0x4]; - __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ - __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ - __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ - __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ - RoReg8 Reserved3[0x20]; - __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ - __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ - __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved4[0x4]; - __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ - __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ - __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ - __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ - __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ - __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ - __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ - __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ - __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ - __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ - __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ - __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ - __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ - __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ - __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ - __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ - __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ - __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ - __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ - __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ - __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ - __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ - RoReg8 Reserved5[0x8]; - __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ - __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ - __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ -} Can; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ - __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ - __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ -} CanMramRxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf0e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ - __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ - __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ -} CanMramRxf0e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf1e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ - __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ - __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ -} CanMramRxf1e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_sidfe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ -} CanMramSidfe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ - __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ - __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ -} CanMramTxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txefe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ - __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ -} CanMramTxefe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_xifde hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ - __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ -} CanMramXifde -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SECTION_CAN_MRAM_RXBE - -#define SECTION_CAN_MRAM_RXF0E - -#define SECTION_CAN_MRAM_RXF1E - -#define SECTION_CAN_MRAM_SIDFE - -#define SECTION_CAN_MRAM_TXBE - -#define SECTION_CAN_MRAM_TXEFE - -#define SECTION_CAN_MRAM_XIFDE - -/*@}*/ - -#endif /* _SAMD51_CAN_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h deleted file mode 100644 index 890e81edf6..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CCL_COMPONENT_ -#define _SAMD51_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x110 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ -#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ - uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ -#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h deleted file mode 100644 index 92fa6813ef..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h +++ /dev/null @@ -1,357 +0,0 @@ -/** - * \file - * - * \brief Component description for CMCC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CMCC_COMPONENT_ -#define _SAMD51_CMCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CMCC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */ -/*@{*/ - -#define CMCC_U2015 -#define REV_CMCC 0x600 - -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ - uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ - uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ - uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ - uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ - uint32_t :18; /*!< bit: 14..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_TYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ -#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ - -#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ -#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) -#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ -#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) -#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ -#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) -#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ -#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ - -/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ - uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ -#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ - -#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ -#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) -#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ -#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) -#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ -#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ - -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ -#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ - -#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ -#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) -#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ - -/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_SR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ -#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ - -#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ -#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) -#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ - -/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_LCKWAY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ -#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ - -#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) -#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ - -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ -#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ - -#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ -#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) -#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ - -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ - uint32_t :16; /*!< bit: 12..27 Reserved */ - uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ -#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ - -#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) -#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) -#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ - -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ -#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ - -#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ - -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ -#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ - -#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) -#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ - -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ -#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ - -#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ -#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) -#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ - -/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ -#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ - -#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ -#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) -#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ - -/** \brief CMCC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ - __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ - __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ - __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ - __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ - RoReg8 Reserved1[0xC]; - __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ - __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ - __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ - __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ - __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ - __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h deleted file mode 100644 index c67efda303..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h +++ /dev/null @@ -1,544 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DAC_COMPONENT_ -#define _SAMD51_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2502 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ - uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ -#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) -#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ -#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) -#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) -#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) -#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) -#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) -#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) -#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) -#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) -#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) -#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) -#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) -#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) -#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) -#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) -#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) -#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) -#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) -#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) -#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) -#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ - __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ - __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ - __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ - __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ -#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) -#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ -#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) -#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) -#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) -#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ -#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) -#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ -#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) -#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) -#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) -#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :1; /*!< bit: 12 Reserved */ - uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ -#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ -#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) -#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ -#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) -#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ -#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) -#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ -#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) -#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) -#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ -#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) -#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ -#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ -#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ - -#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ -#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) -#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ - -/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ -#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ - -#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ -#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) -#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ - __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ - __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ - __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ - __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x3]; - __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h deleted file mode 100644 index 295b31fe48..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h +++ /dev/null @@ -1,1416 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DMAC_COMPONENT_ -#define _SAMD51_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2503 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t :6; /*!< bit: 2.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ -#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) -#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ -#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ -#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ - uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ - uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ - uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ - uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ - uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ - uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ - uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ - uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ - uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ - uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ - uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ - uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ - uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ - uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ - uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ - uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ - uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ - uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ - uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ -#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) -#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ -#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) -#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ -#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) -#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ -#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) -#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ -#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ - uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ - uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ - uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ - uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ - uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ - uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ - uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ - uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ - uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ - uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ - uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ - uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ - uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ - uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ - uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) -#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) -#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) -#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) -#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) -#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) -#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) -#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) -#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) -#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) -#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) -#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) -#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) -#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) -#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) -#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ - uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ - uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ - uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ - uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ - uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ - uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ - uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ - uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ - uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ - uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ - uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ - uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ - uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ - uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ - uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ -#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) -#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ -#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) -#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ -#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) -#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ -#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) -#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ -#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) -#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ -#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) -#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ -#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) -#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ -#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) -#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ -#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) -#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ -#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) -#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ -#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) -#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ -#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) -#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ -#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) -#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ -#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) -#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ -#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) -#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ -#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ - uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ - uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ - uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ - uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ - uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ - uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ - uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ - uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ - uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ - uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ - uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ - uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ - uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ - uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ - uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ -#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) -#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ -#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) -#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ -#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) -#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ -#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) -#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ -#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) -#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ -#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) -#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ -#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) -#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ -#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) -#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ -#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) -#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ -#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) -#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ -#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) -#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ -#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) -#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ -#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) -#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ -#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) -#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ -#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) -#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ -#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ - uint32_t :5; /*!< bit: 15..19 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ - uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ -#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) -#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ -#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ -#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) -#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ -#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ -#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ -#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) -#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ -#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ -#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) -#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ -#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ - -#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHPRILVL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ -#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ - -#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ -#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) -#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ -#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ -#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ -#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ -#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ -#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ -#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ - -/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ - uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ - uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHEVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ -#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ - -#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ -#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) -#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ -#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ -#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ -#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ -#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ -#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ -#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ -#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ -#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) -#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ -#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) -#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ -#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits -#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 10 // Index of Generic Clock -#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value -#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value -#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented -#define USB_PIPE_NUM 8 // Number of USB pipes -#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system -#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) -#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode -#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested -#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode - -#endif /* _SAMD51_USB_INSTANCE_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h deleted file mode 100644 index 98a2ca13d7..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_WDT_INSTANCE_ -#define _SAMD51_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAMD51_WDT_INSTANCE_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h deleted file mode 100644 index d8fa56d5ba..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h +++ /dev/null @@ -1,1863 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_PIO_ -#define _SAMD51J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J18A_PIO_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h deleted file mode 100644 index 9009b6d653..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) - #include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) - #include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) - #include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) - #include "samd51j19a.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) - #include "samd51j20a.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) - #include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) - #include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) - #include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) - #include "samd51p20a.h" -#else - #error Library does not support the specified device -#endif - -#endif /* _SAM_ */ - diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h deleted file mode 100644 index d08ac64cb8..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAMD51 - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ -#define _SAMD51_ - -/** - * \defgroup SAMD51_definitions SAMD51 Device Definitions - * \brief SAMD51 CMSIS Definitions. - */ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) - #include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) - #include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) - #include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) - #include "samd51j19a.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) - #include "samd51j20a.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) - #include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) - #include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) - #include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) - #include "samd51p20a.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAMD51_ */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h deleted file mode 100644 index 5cfccdfc84..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h +++ /dev/null @@ -1,1079 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51J18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_ -#define _SAMD51J18A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions - * This file defines all structures and symbols for SAMD51J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51J18A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51J18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060006) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J18A_H */ diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h deleted file mode 100644 index cfbd2b921b..0000000000 --- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD51_H_INCLUDED_ -#define _SYSTEM_SAMD51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD51_H_INCLUDED */ diff --git a/lib/python/qmk/info.py b/lib/python/qmk/info.py index 72b19a9fec..0c6dd181d9 100644 --- a/lib/python/qmk/info.py +++ b/lib/python/qmk/info.py @@ -898,9 +898,6 @@ def arm_processor_rules(info_data, rules): info_data['platform'] = 'STM32' elif 'MCU_SERIES' in rules: info_data['platform'] = rules['MCU_SERIES'] - elif 'ARM_ATSAM' in rules: - info_data['platform'] = 'ARM_ATSAM' - info_data['platform_key'] = 'arm_atsam' return info_data -- cgit v1.2.3