diff options
| author | Joel Challis | 2025-10-13 07:40:45 +0200 |
|---|---|---|
| committer | GitHub | 2025-10-13 07:40:45 +0200 |
| commit | f4068dbfb0a5bc8ba0daf4e714ff3cbe89ef92c2 (patch) | |
| tree | 3007957050a8259df41d1d7f399faeeb088be5e7 /platforms/chibios | |
| parent | 08405df1505293acb9a4e89bcf98935d78902094 (diff) | |
Update STM32F446 default HSE to 8MHz (#25717)
Diffstat (limited to 'platforms/chibios')
3 files changed, 3 insertions, 3 deletions
diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h index f05762c9b4..b06d96b5d7 100644 --- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h +++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h @@ -15,7 +15,6 @@ */ #pragma once -#define STM32_HSECLK 16000000 // The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix: #define BOARD_OTG_NOVBUSSENS diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h index 362327efde..9af5c14d52 100644 --- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h +++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h @@ -13,6 +13,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#pragma once #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP # define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h index 566c146c25..9c5cb82436 100644 --- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h @@ -48,7 +48,7 @@ #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 +#define STM32_PLLM_VALUE 4 #define STM32_PLLN_VALUE 180 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 @@ -58,7 +58,7 @@ #define STM32_PLLI2SP_VALUE 4 #define STM32_PLLI2SQ_VALUE 4 #define STM32_PLLSAIN_VALUE 192 -#define STM32_PLLSAIM_VALUE 8 +#define STM32_PLLSAIM_VALUE 4 #define STM32_PLLSAIP_VALUE 8 #define STM32_PLLSAIQ_VALUE 4 #define STM32_HPRE STM32_HPRE_DIV1 |